High Performance Embedded Architectures and Compilers Second International Conference, HiPEAC 2007, Ghent, Belgium, January 2007, Proceedings

Name: High Performance Embedded Architectures and Compilers Second International Conference, HiPEAC 2007, Ghent, Belgium, January 2007, Proceedings
Price: 22.5 USD
Availability: InStock
ISBN: 9783540693376

ISBN-10: 3540693378

ISBN-13: 9783540693376

Edition: 2007

Authors: Koen de Bosschere, David Kaeli, Per Stenstrï¿½m, Theo Ungerer, David Whalley

List price: $54.99

30 day, 100% satisfaction guarantee!

Marketplace

4 new & used from $22.50

what's this?

Rush Rewards U
Members Receive:

You have reached 400 XP and carrot coins. That is the daily max!

Description:

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007. The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems.

Book details

List price: $54.99
Copyright year: 2007
Publisher: Springer Berlin / Heidelberg
Publication date: 1/12/2007
Binding: Paperback
Pages: 307
Size: 6.10" wide x 9.25" long x 0.75" tall
Weight: 2.222



Abstract of keynote : insight, not (random) numbers : an embedded perspective



Compiler-assisted memory encryption for embedded processors



Leveraging high performance data cache techniques to save power in embedded systems



Applying decay to reduce dynamic power in set-associative caches



Virtual registers : reducing register pressure without enlarging the register file



Bounds checking with taint-based analysis



Reducing exit stub memory consumption in code caches



Reducing branch misprediction penalties via adaptive pipeline scaling



Fetch gating control through speculative instruction window weighting



Dynamic capacity-speed tradeoffs in SMT processor caches



Branch history matching : branch predictor warmup for sampled simulation



Sunflower : full-system, embedded microarchitecture evaluation



Efficient program power behavior characterization



Performance/energy optimization of DSP transforms on the XScale processor



Arx : a toolset for the efficient simulation and direct synthesis of high-performance signal processing algorithms



A throughput-driven task creation and mapping for network processors



MiDataSets : creating the conditions for a more realistic evaluation of iterative optimization



Evaluation of offset assignment heuristics



Customizing the datapath and ISA of soft VLIW processors



Instruction set extension generation with considering physical constraints