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| Preface | |
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| Introduction to Reconfigurable Computing | |
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| Why Reconfigurable Computing? | |
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| What is Reconfigurable Computing? | |
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| From Codesign to Reconfiguration | |
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| Reconfiguration Technology | |
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| Reconfiguration Tools and Platforms | |
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| Design and Verification Methodologies | |
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| Application Examples | |
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| Embedded Systems | |
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| Network Security Applications | |
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| Multimedia Applications | |
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| Scientific Computing | |
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| Reconfigurable SAT Solvers | |
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| FPGA Technology and Dynamic Reconfiguration | |
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| FPGA Overview | |
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| FPGA Architecture | |
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| The Configuration Bitstream | |
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| Overall Bitstream Structure | |
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| Packet Headers | |
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| Configuration Registers | |
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| Frame Indexing | |
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| FPGA Families and Models | |
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| Spartan 3 | |
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| Virtex II Pro | |
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| Virtex 4 | |
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| Configuration Conventions and File Formats | |
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| Configuration Resources Numbering Scheme | |
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| The RPM Grid | |
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| UCF File Format | |
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| A Bird's-Eye View of Reconfigurable Systems | |
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| Reconfiguration Characterization | |
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| Complete vs. Partial Reconfiguration: An Overview of Different Techniques | |
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| Reconfigurable Architectures: The Five Ws | |
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| Reconfigurable Architecture Examples | |
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| Reconfigurable Hardware Design | |
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| Model | |
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| Partitioning for Reconfigurable Architectures | |
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| Temporal Partitioning Approaches | |
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| Spatial and Temporal Partitioning Approaches | |
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| Regularity Extraction | |
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| Tree-Shaped Recurrent Structure Detection | |
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| The DRESD Partitioning-Based Approach | |
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| Scheduling Techniques | |
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| Related Work | |
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| ILP Formulation | |
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| Heuristic | |
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| Operating System for Reconfigurable Systems | |
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| Motivation for OS4RS | |
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| Requirements for OS4RS | |
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| Layered Architecture for OS4RS | |
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| Hardware Layer | |
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| Configuration Layer | |
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| Placement Layer | |
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| Scheduling Layer | |
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| Module Layer | |
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| Application Layer | |
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| OS4RS Examples | |
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| Dynamic Reconfigurable Systems Design Flows | |
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| System Design Flows | |
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| Basic Flows | |
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| Generic Flows | |
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| Reconfigurable System Design Flow: Structure and Implementation | |
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| The Hardware Side of the Design Flow | |
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| System Description Phase | |
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| Design Synthesis and Placement Constraints Assignment Phase | |
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| System Generation Phase | |
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| Reconfigurable System Verification | |
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| System-Level Verification Techniques | |
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| Formal Verification | |
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| Language Approach | |
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| Hardware-Software Coverification | |
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| Hardware-Software Co-Simulation | |
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| Hardware-Software Prototyping | |
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| Reconfigurable System Simulation Frameworks | |
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| Overview of Frameworks | |
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| Perfecto Framework | |
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| Reconfigurable Architecture Model | |
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| Application Model | |
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| Partitioning | |
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| Scheduling | |
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| Placement | |
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| Performance Evaluation Results | |
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| Application Examples | |
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| Dynamically Partially Reconfigurable System Design Implementation | |
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| Partial Reconfiguration on Xilinx Virtex Family FPGAs | |
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| Early Access Partial Reconfiguration Design Flow | |
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| Design Partitioning and Synthesis | |
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| Design Budgeting | |
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| Non-PR Design | |
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| Top-Level Implementation | |
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| Static Logic Implementation | |
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| PR Block Implementation | |
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| Merge | |
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| Creating Partially Reconfigurable Hardware Design | |
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| Software-Controlled Partially Reconfigurable Design | |
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| Operating System for Reconfigurable Systems | |
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| References | |
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| Index | |