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Reconfigurable System Design and Verification

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ISBN-10: 1420062662

ISBN-13: 9781420062663

Edition: 2009

Authors: Marco D. Santambrogio, Pao-Ann Hsiung, Chun-Hsian Huang

List price: $119.95
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Description:

Focusing on system-level design and verification techniques, this text allows readers to immediately grasp concepts and put them into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrate…    
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Book details

List price: $119.95
Copyright year: 2009
Publisher: CRC Press LLC
Publication date: 2/17/2009
Binding: Hardcover
Pages: 268
Size: 6.25" wide x 9.50" long x 0.75" tall
Weight: 1.298
Language: English

Preface
Introduction to Reconfigurable Computing
Why Reconfigurable Computing?
What is Reconfigurable Computing?
From Codesign to Reconfiguration
Reconfiguration Technology
Reconfiguration Tools and Platforms
Design and Verification Methodologies
Application Examples
Embedded Systems
Network Security Applications
Multimedia Applications
Scientific Computing
Reconfigurable SAT Solvers
FPGA Technology and Dynamic Reconfiguration
FPGA Overview
FPGA Architecture
The Configuration Bitstream
Overall Bitstream Structure
Packet Headers
Configuration Registers
Frame Indexing
FPGA Families and Models
Spartan 3
Virtex II Pro
Virtex 4
Configuration Conventions and File Formats
Configuration Resources Numbering Scheme
The RPM Grid
UCF File Format
A Bird's-Eye View of Reconfigurable Systems
Reconfiguration Characterization
Complete vs. Partial Reconfiguration: An Overview of Different Techniques
Reconfigurable Architectures: The Five Ws
Reconfigurable Architecture Examples
Reconfigurable Hardware Design
Model
Partitioning for Reconfigurable Architectures
Temporal Partitioning Approaches
Spatial and Temporal Partitioning Approaches
Regularity Extraction
Tree-Shaped Recurrent Structure Detection
The DRESD Partitioning-Based Approach
Scheduling Techniques
Related Work
ILP Formulation
Heuristic
Operating System for Reconfigurable Systems
Motivation for OS4RS
Requirements for OS4RS
Layered Architecture for OS4RS
Hardware Layer
Configuration Layer
Placement Layer
Scheduling Layer
Module Layer
Application Layer
OS4RS Examples
Dynamic Reconfigurable Systems Design Flows
System Design Flows
Basic Flows
Generic Flows
Reconfigurable System Design Flow: Structure and Implementation
The Hardware Side of the Design Flow
System Description Phase
Design Synthesis and Placement Constraints Assignment Phase
System Generation Phase
Reconfigurable System Verification
System-Level Verification Techniques
Formal Verification
Language Approach
Hardware-Software Coverification
Hardware-Software Co-Simulation
Hardware-Software Prototyping
Reconfigurable System Simulation Frameworks
Overview of Frameworks
Perfecto Framework
Reconfigurable Architecture Model
Application Model
Partitioning
Scheduling
Placement
Performance Evaluation Results
Application Examples
Dynamically Partially Reconfigurable System Design Implementation
Partial Reconfiguration on Xilinx Virtex Family FPGAs
Early Access Partial Reconfiguration Design Flow
Design Partitioning and Synthesis
Design Budgeting
Non-PR Design
Top-Level Implementation
Static Logic Implementation
PR Block Implementation
Merge
Creating Partially Reconfigurable Hardware Design
Software-Controlled Partially Reconfigurable Design
Operating System for Reconfigurable Systems
References
Index