Skip to content

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters Analysis, Design and Tradeoffs

Spend $50 to get a free movie!

ISBN-10: 1402097158

ISBN-13: 9781402097157

Edition: 2009

Authors: Pedro M. Figueiredo, Jo�o C. Vital

List price: $159.99
Blue ribbon 30 day, 100% satisfaction guarantee!
Out of stock
what's this?
Rush Rewards U
Members Receive:
Carrot Coin icon
XP icon
You have reached 400 XP and carrot coins. That is the daily max!

Customers also bought

Book details

List price: $159.99
Copyright year: 2009
Publisher: Springer London, Limited
Publication date: 3/9/2009
Binding: Hardcover
Pages: 382
Size: 6.50" wide x 9.50" long x 1.00" tall
Weight: 1.584
Language: English

Pedro Figueiredo received the degrees of Licenciado and Doutor (PhD) in Electrical and Computer Engineering in 1999 and 2006, respectively, from the Instituto Superior Técnico (IST), Lisbon, Portugal. From 1997 to 1999, he was with the Analog and Mixed-Mode Circuits Group in the Institute for Systems and Computer Engineering (INESC), Lisbon, Portugal, where he worked on low-noise logic families and high-speed Analog-to-Digital Converters.In 1999, he joined Chipidea - Microelectrónica, where he currently leads the group responsible for the design of Analog-to-Digital Converters. His main research interests are in the area of analog and mixed-signal circuits, with emphasis on high-speed…    

Preface
List of Symbols and Abbreviations
High-Speed ADC Architectures
Introduction
The Analog-to-Digital Converter
Flash ADCs
Two-Step Flash ADCs
Folding and Interpolation ADCs
Building Blocks of CMOS High-Speed ADCs
Averaging Technique - DC Analysis and Termination
Introduction
Published Studies on the Averaging Technique
Output Voltage and Gain
Effect of Mismatches - INL and DNL
Averaging in Folding Circuits
Considerations About the Yield
Termination of the Averaging Network
Averaging Technique - Transient Analysis and Automated Design
Introduction
Flash ADC Architecture
Output Voltage and Gain
Effect of Mismatches
Design of Averaged Pre-Amplifier Stages in Flash ADCs
Integrated Prototypes using Averaging
Introduction
7-bit 120 MS/s I/Q flash ADC
10-bit 100 MS/s Folding and Interpolation ADC
Offset Cancellation Methods
Introduction
Offset Cancellation Techniques
New Offset Cancellation Technique
6-bit 1 GHz Two-Step Subranging ADC
Conclusions
Overview of the Research Work
Averaging with Piecewise Linear Differential Pairs
Introduction
Output Voltage and Gain
Effect of Mismatches - INL and DNL
Mismatches in the Resistors of the Aveaging Network
Introduction
Mismatches in Resistors R.0
Mismatches in Resistors R1
Averaging in Folding Stages
Introduction
Equivalence Between Circular and Infinite Networks
Output Voltage and Gain
Effect of Mismatches
References
Index