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Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

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ISBN-10: 1402085745

ISBN-13: 9781402085741

Edition: 2008

Authors: Andreas Wieferink, Rainer Leupers, Heinrich Meyr

List price: $159.99
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Description:

The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration…    
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Book details

List price: $159.99
Copyright year: 2008
Publisher: Springer
Publication date: 7/15/2008
Binding: Hardcover
Pages: 162
Size: 6.25" wide x 9.25" long x 0.50" tall
Weight: 0.880

Both Prof. Heinrich Meyr and Prof. Rainer Leupers have (co-)authored numerous books for Springer

Introduction
Challenge: From Board to SoC
Degrees of SoC Customization
Organization of this Book
SoC Design Methodologies
Traditional HW/SW Co-Design
System Level Design
Current Research on SoC Design Methodologies
Contribution of this Work
Communication Modeling
Transaction Level Modeling
Generic Communication Modeling
Communication Customization
The BusCompiler Tool
Processor Modeling
Generic Processor Modeling
Processor Customization Techniques
LISA
Processor System Integration
Simulator Structure
Adaptors: Bridging Abstraction Gaps
Commercial SoC Simulation Environments
Successive Top-Down Refinement Flow
Phase 1: Standalone
Phase 2: IA ASIP [actual symbol not reproducible] AVF Communication Models
Phase 3: IA ASIP [actual symbol not reproducible] CA TLM Bus
Phase 4: CA ASIP [actual symbol not reproducible] CA TLM Bus
Phase 5: BCA ASIP [actual symbol not reproducible] CA TLM Bus
Phase 6: RTL ASIP [actual symbol not reproducible] CA TLM Bus
Phase 7: RTL ASIP [actual symbol not reproducible] RTL Bus
Automatic Retargetability
MP-SoC Simulator Generation Chain
Structure of the Generated Simulator
Bus Interface Specification
Debugging and Profiling
Multi-Processor Debugger
TLM Bus Traffic Visualization
Bus Interface Analysis
Case Study
Multi Processor JPEG Decoding Platform
Phase 2: IA + AVF Platform
Phase 3: LA + BusCompiler Platform
Phase 4: CA + BusCompiler Platform
Phase 5: BCA + BusCompiler Platform
Summary
Businterface Definition Files
Extended CoWare Tool Flow
List of Figures
References
Index