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Direct Transistor-Level Layout for Digital Blocks

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ISBN-10: 1402076657

ISBN-13: 9781402076657

Edition: 2004

Authors: Prakash Gopalakrishnan, Rob A. Rutenbar

List price: $169.99
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Description:

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early…    
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Book details

List price: $169.99
Copyright year: 2004
Publisher: Springer
Publication date: 6/17/2004
Binding: Hardcover
Pages: 125
Size: 6.25" wide x 9.25" long x 0.50" tall
Weight: 0.792

Introduction
Circuit structure and clustering
Global placement
Detailed placement and layout results
Timing-driven placement
Conclusion