Skip to content

Verilog� Hardware Description Language

Spend $50 to get a free DVD!

ISBN-10: 1402070896

ISBN-13: 9781402070891

Edition: 5th 2002 (Revised)

Authors: Philip R. Moorby, Donald E. Thomas

List price: $159.00
Shipping box This item qualifies for FREE shipping.
Blue ribbon 30 day, 100% satisfaction guarantee!
what's this?
Rush Rewards U
Members Receive:
Carrot Coin icon
XP icon
You have reached 400 XP and carrot coins. That is the daily max!

Customers also bought

Book details

List price: $159.00
Edition: 5th
Copyright year: 2002
Publisher: Springer
Publication date: 6/30/2002
Binding: Hardcover
Pages: 382
Size: 6.75" wide x 9.75" long x 1.00" tall
Weight: 1.540
Language: English

Preface
From the Old to the New
Acknowledgments
Verilog - A Tutorial Introduction
Getting Started
A Structural Description
Simulating the binaryToESeg Driver
Creating Ports For the Module
Creating a Testbench For a Module
Behavioral Modeling of Combinational Circuits
Procedural Models
Rules for Synthesizing Combinational Circuits
Procedural Modeling of Clocked Sequential Circuits
Modeling Finite State Machines
Rules for Synthesizing Sequential Systems
Non-Blocking Assignment ("<=")
Module Hierarchy
The Counter
A Clock for the System
Tying the Whole Circuit Together
Tying Behavioral and Structural Models Together
Summary
Exercises
Logic Synthesis
Overview of Synthesis
Register-Transfer Level Systems
Disclaimer
Combinational Logic Using Gates and Continuous Assign
Procedural Statements to Specify Combinational Logic
The Basics
Complications--Inferred Latches
Using Case Statements
Specifying Don't Care Situations
Procedural Loop Constructs
Inferring Sequential Elements
Latch Inferences
Flip Flop Inferences
Summary
Inferring Tri-State Devices
Describing Finite State Machines
An Example of a Finite State Machine
An Alternate Approach to FSM Specification
Finite State Machine and Datapath
A Simple Computation
A Datapath For Our System
Details of the Functional Datapath Modules
Wiring the Datapath Together
Specifying the FSM
Summary on Logic Synthesis
Exercises
Behavioral Modeling
Process Model
If-Then-Else
Where Does The ELSE Belong?
The Conditional Operator
Loops
Four Basic Loop Statements
Exiting Loops on Exceptional Conditions
Multi-way Branching
If-Else-If
Case
Comparison of Case and If-Else-If
Casez and Casex
Functions and Tasks
Tasks
Functions
A Structural View
Rules of Scope and Hierarchical Names
Rules of Scope
Hierarchical Names
Summary
Exercises
Concurrent Processes
Concurrent Processes
Events
Event Control Statement
Named Events
The Wait Statement
A Complete Producer-Consumer Handshake
Comparison of the Wait and While Statements
Comparison of Wait and Event Control Statements
A Concurrent Process Example
A Simple Pipelined Processor
The Basic Processor
Synchronization Between Pipestages
Disabling Named Blocks
Intra-Assignment Control and Timing Events
Procedural Continuous Assignment
Sequential and Parallel Blocks
Exercises
Module Hierarchy
Module Instantiation and Port Specifications
Parameters
Arrays of Instances
Generate Blocks
Exercises
Logic Level Modeling
Introduction
Logic Gates and Nets
Modeling Using Primitive Logic Gates
Four-Level Logic Values
Nets
A Logic Level Example
Continuous Assignment
Behavioral Modeling of Combination Circuits
Net and Continuous Assign Declarations
A Mixed Behavioral/Structural Example
Logic Delay Modeling
A Gate Level Modeling Example
Gate and Net Delays
Specifying Time Units
Minimum, Typical, and Maximum Delays
Delay Paths Across a Module
Summary of Assignment Statements
Summary
Exercises
Cycle-Accurate Specification
Cycle-Accurate Behavioral Descriptions
Specification Approach
A Few Notes
Cycle-Accurate Specification
Inputs and Outputs of an Always Block
Input/Output Relationships of an Always Block
Specifying the Reset Function
Mealy/Moore Machine Specifications
A Complex Control Specification
Data and Control Path Trade-offs
Introduction to Behavioral Synthesis
Summary
Advanced Timing
Verilog Timing Models
Basic Model of a Simulator
Gate Level Simulation
Towards a More General Model
Scheduling Behavioral Models
Non-Deterministic Behavior of the Simulation Algorithm
Near a Black Hole
It's a Concurrent Language
Non-Blocking Procedural Assignments
Contrasting Blocking and Non-Blocking Assignments
Prevalent Usage of the Non-Blocking Assignment
Extending the Event-Driven Scheduling Algorithm
Illustrating Non-Blocking Assignments
Summary
Exercises
User-Defined Primitives
Combinational Primitives
Basic Features of User-Defined Primitives
Describing Combinational Logic Circuits
Sequential Primitives
Level-Sensitive Primitives
Edge-Sensitive Primitives
Shorthand Notation
Mixed Level- and Edge-Sensitive Primitives
Summary
Exercises
Switch Level Modeling
A Dynamic MOS Shift Register Example
Switch Level Modeling
Strength Modeling
Strength Definitions
An Example Using Strengths
Resistive MOS Gates
Ambiguous Strengths
Illustrations of Ambiguous Strengths
The Underlying Calculations
The miniSim Example
Overview
The miniSim Source
Simulation Results
Summary
Exercises
Projects
Modeling Power Dissipation
Modeling Power Dissipation
What to do
Steps
A Floppy Disk Controller
Introduction
Disk Format
Function Descriptions
Reality Sets In...
Everything You Always Wanted to Know about CRC's
Supporting Verilog Modules
Tutorial Questions and Discussion
Structural Descriptions
Testbench Modules
Combinational Circuits Using always
Sequential Circuits
Hierarchical Descriptions
Lexical Conventions
White Space and Comments
Operators
Numbers
Strings
Identifiers, System Names, and Keywords
Verilog Operators
Table of Operators
Operator Precedence
Operator Truth Tables
Expression Bit Lengths
Verilog Gate Types
Logic Gates
BUF and NOT Gates
BUFIF and NOTIF Gates
MOS Gates
Bidirectional Gates
CMOS Gates
Pullup and Pulldown Gates
Registers, Memories, Integers, and Time
Registers
Memories
Integers and Times
System Tasks and Functions
Display and Write Tasks
Continuous Monitoring
Strobed Monitoring
File Output
Simulation Time
Stop and Finish
Random
Reading Data From Disk Files
Formal Syntax Definition
Tutorial Guide to Formal Syntax Specification
Source text
Declarations
Primitive instances
Module and generated instantiation
UDP declaration and instantiation
Behavioral statements
Specify section
Expressions
General
Index