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| List of Figures | |
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| Preface | |
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| Acknowledgments | |
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| First Author's Personal Thanks | |
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| Preliminaries | |
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| High-speed CMOS-circuits | |
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| Asynchronous protocols and delay-insensitive codes | |
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| Production rules | |
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| The MiniMIPS processor | |
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| Commonly used abbreviations | |
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| Asynchronous-Pulse-Logic Basics | |
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| Road map of this chapter | |
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| The pulse repeater | |
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| Timing constraints in the pulse repeater | |
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| Simulating the pulse repeater | |
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| The synchronous digital model | |
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| Asymmetric pulse-repeaters | |
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| Formal model of pulse repeater | |
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| Basic definitions | |
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| Handling the practical simulations | |
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| Expanding the model | |
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| Using the extended model | |
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| Noise margins | |
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| Differential-equations treatment of pulse repeater | |
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| Input behavior of pulse repeater | |
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| Generalizations and restrictions | |
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| Computing with Pulses | |
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| A simple logic example | |
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| Pulse-handshake duty-cycle | |
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| Single-track-handshake interfaces | |
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| Timing constraints and timing "assumptions" | |
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| Minimum cycle-transition-counts | |
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| Solutions to transition-count problem | |
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| The APL design-style in short | |
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| A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuits | |
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| Preliminaries | |
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| Transition counting in pipelined asynchronous circuits | |
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| Transition-count choices in pulsed circuits | |
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| Execution model | |
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| Capabilities of the STAPL family | |
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| Design philosophy | |
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| The basic template | |
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| Bit generator | |
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| Bit bucket | |
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| Left-right buffer | |
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| Summary of properties of the simple circuits | |
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| A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuits | |
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| Multiple input and output channels | |
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| Naive implementation | |
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| Double triggering of logic block in the naive design | |
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| Solution | |
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| Timing assumptions | |
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| General logic computations | |
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| Inputs whose values are not used | |
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| Conditional communications | |
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| The same program can be expressed in several ways | |
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| Simple techniques for sends | |
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| General techniques for conditional communications | |
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| Storing state | |
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| The general state-storing problem | |
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| Implementing state variables | |
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| Compiling the state bit | |
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| Special circuits | |
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| Arbitration | |
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| Four-phase converters | |
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| Resetting STAPL circuits | |
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| Previously used resetting schemes | |
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| An example | |
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| Generating initial tokens | |
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| How our circuits relate to the design philosophy | |
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| Noise | |
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| External noise-sources | |
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| Charge sharing | |
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| Crosstalk | |
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| Design inaccuracies | |
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| Automatic Generation of Asynchronous-Pulse-Logic Circuits | |
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| Straightforwardly compiling from a higher-level specification | |
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| An alternative compilation method | |
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| What we compile | |
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| The PL1 language | |
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| Channels or shared variables? | |
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| Simple description of the PL1 language | |
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| An example: the replicator | |
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| Compiling PL1 | |
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| PL1-compiler front-end | |
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| Determinism conditions | |
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| Data encoding | |
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| PL1-compiler back-end | |
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| Slack | |
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| Logic simplification | |
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| Code generation | |
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| A Design Example: The Spam Microprocessor | |
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| The SPAM architecture | |
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| SPAM implementation | |
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| Decomposition | |
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| Arbitrated branch-delay | |
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| Byte skewing | |
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| Design examples | |
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| The PCUNIT | |
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| The REGFILE | |
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| Performance measurements on the SPAM implementation | |
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| Straightline program | |
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| Computing Fibonacci numbers | |
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| Energy measurements | |
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| Summary of SPAM implementation's performance | |
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| Comparison with QDI | |
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| Related Work | |
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| Theory | |
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| STAPL circuit family | |
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| PL1 language | |
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| SPAM microprocessor | |
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| Lessons Learned | |
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| Conclusion | |
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| Appendices | |
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| PL1 Report | |
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| Scope | |
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| Structure of PL1 | |
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| Syntax elements | |
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| Keywords | |
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| Comments | |
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| Numericals | |
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| Identifiers | |
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| Reserved special operators | |
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| Expression operators | |
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| Expression syntax | |
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| Actions | |
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| PL1 process description | |
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| Declarations | |
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| Communication statement | |
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| Process communication-block | |
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| Semantics | |
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| Expression semantics | |
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| Action semantics | |
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| Execution semantics | |
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| Invariants | |
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| Semantics in terms of CHP | |
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| Slack elasticity | |
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| Examples | |
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| SPAM Processor Architecture Definition | |
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| SPAM overview | |
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| SPAM instruction format | |
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| SPAM instruction semantics | |
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| Operand generation | |
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| Operation definitions | |
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| Assembly-language conventions | |
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| The SPAM assembly format | |
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| Proof that Definition 2.2 Defines a Partial Order | |
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| Remark on Continuity | |