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Asynchronous Pulse Logic

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ISBN-10: 1402070683

ISBN-13: 9781402070686

Edition: 2002

Authors: Mika Nystrom, Alain J. Martin

List price: $109.99
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Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family. Asynchronous Pulse Logic will be of interest to industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this useful reference for computer-aided design of asynchronous or related VLSI systems.
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Book details

List price: $109.99
Copyright year: 2002
Publisher: Springer
Publication date: 5/31/2002
Binding: Hardcover
Pages: 206
Size: 6.10" wide x 9.25" long x 0.75" tall
Weight: 2.464
Language: English

List of Figures
First Author's Personal Thanks
High-speed CMOS-circuits
Asynchronous protocols and delay-insensitive codes
Production rules
The MiniMIPS processor
Commonly used abbreviations
Asynchronous-Pulse-Logic Basics
Road map of this chapter
The pulse repeater
Timing constraints in the pulse repeater
Simulating the pulse repeater
The synchronous digital model
Asymmetric pulse-repeaters
Formal model of pulse repeater
Basic definitions
Handling the practical simulations
Expanding the model
Using the extended model
Noise margins
Differential-equations treatment of pulse repeater
Input behavior of pulse repeater
Generalizations and restrictions
Computing with Pulses
A simple logic example
Pulse-handshake duty-cycle
Single-track-handshake interfaces
Timing constraints and timing "assumptions"
Minimum cycle-transition-counts
Solutions to transition-count problem
The APL design-style in short
A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuits
Transition counting in pipelined asynchronous circuits
Transition-count choices in pulsed circuits
Execution model
Capabilities of the STAPL family
Design philosophy
The basic template
Bit generator
Bit bucket
Left-right buffer
Summary of properties of the simple circuits
A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuits
Multiple input and output channels
Naive implementation
Double triggering of logic block in the naive design
Timing assumptions
General logic computations
Inputs whose values are not used
Conditional communications
The same program can be expressed in several ways
Simple techniques for sends
General techniques for conditional communications
Storing state
The general state-storing problem
Implementing state variables
Compiling the state bit
Special circuits
Four-phase converters
Resetting STAPL circuits
Previously used resetting schemes
An example
Generating initial tokens
How our circuits relate to the design philosophy
External noise-sources
Charge sharing
Design inaccuracies
Automatic Generation of Asynchronous-Pulse-Logic Circuits
Straightforwardly compiling from a higher-level specification
An alternative compilation method
What we compile
The PL1 language
Channels or shared variables?
Simple description of the PL1 language
An example: the replicator
Compiling PL1
PL1-compiler front-end
Determinism conditions
Data encoding
PL1-compiler back-end
Logic simplification
Code generation
A Design Example: The Spam Microprocessor
The SPAM architecture
SPAM implementation
Arbitrated branch-delay
Byte skewing
Design examples
Performance measurements on the SPAM implementation
Straightline program
Computing Fibonacci numbers
Energy measurements
Summary of SPAM implementation's performance
Comparison with QDI
Related Work
STAPL circuit family
PL1 language
SPAM microprocessor
Lessons Learned
PL1 Report
Structure of PL1
Syntax elements
Reserved special operators
Expression operators
Expression syntax
PL1 process description
Communication statement
Process communication-block
Expression semantics
Action semantics
Execution semantics
Semantics in terms of CHP
Slack elasticity
SPAM Processor Architecture Definition
SPAM overview
SPAM instruction format
SPAM instruction semantics
Operand generation
Operation definitions
Assembly-language conventions
The SPAM assembly format
Proof that Definition 2.2 Defines a Partial Order
Remark on Continuity