| |
| |
| Preface | |
| |
| |
| |
| |
| EquiMax Optimal Scheduling Formulation | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Machine Description | |
| |
| |
| |
| DAG Model | |
| |
| |
| |
| Scheduling Problem | |
| |
| |
| |
| Registers Constraints | |
| |
| |
| |
| Resources Constraints | |
| |
| |
| |
| Integer Linear Programming Techniques | |
| |
| |
| |
| Writing Logical Operators with Linear Constraints | |
| |
| |
| |
| Computing the Maximum with Linear Constraints | |
| |
| |
| |
| EquiMax Integer Programming Formulation | |
| |
| |
| |
| Scheduling Variables and Objective Function | |
| |
| |
| |
| Registers Constraints | |
| |
| |
| |
| Interference Graph | |
| |
| |
| |
| Maximal Clique in the Interference Graph | |
| |
| |
| |
| Resources Constraints | |
| |
| |
| |
| Conflicting Graph | |
| |
| |
| |
| Maximal Click in the Conflicting Graph | |
| |
| |
| |
| Summary | |
| |
| |
| |
| Related Work | |
| |
| |
| |
| Conclusion | |
| |
| |
| |
| An Efficient Semi-Hierarchical Array Layout | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Array Layout | |
| |
| |
| |
| Linear Array Layouts | |
| |
| |
| |
| Hierarchical Array Layouts | |
| |
| |
| |
| Address Arithmetic | |
| |
| |
| |
| Experimental Evaluation | |
| |
| |
| |
| Cache Interference and Conflict Vectors | |
| |
| |
| |
| Cache Interference | |
| |
| |
| |
| Conflict Vectors | |
| |
| |
| |
| Computing Conflict Vectors | |
| |
| |
| |
| Self Interference | |
| |
| |
| |
| Cross Interference | |
| |
| |
| |
| Examples | |
| |
| |
| |
| Related Work | |
| |
| |
| |
| Conclusions | |
| |
| |
| |
| Impact of Tile-Size Selection for Skewed Tiling | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Related Work | |
| |
| |
| |
| Competing Tile-Size Selection Schemes | |
| |
| |
| |
| Other Related Work | |
| |
| |
| |
| Background | |
| |
| |
| |
| Skewed Tiling | |
| |
| |
| |
| Memory Hierarchy | |
| |
| |
| |
| A Memory Cost Model | |
| |
| |
| |
| Tile-Size Selection | |
| |
| |
| |
| An Execution Cost Model for Tiling | |
| |
| |
| |
| Tile-Size Selection Algorithm | |
| |
| |
| |
| Preserving Property 1 | |
| |
| |
| |
| Preserving Property 2 | |
| |
| |
| |
| Algorithm STS | |
| |
| |
| |
| A Running Example | |
| |
| |
| |
| Experimental Evaluation | |
| |
| |
| |
| Discussion | |
| |
| |
| |
| Conclusion | |
| |
| |
| |
| Improving Software Pipelining by Hiding Memory Latency | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Background | |
| |
| |
| |
| Data-Reuse Analysis | |
| |
| |
| |
| Software Pipelining | |
| |
| |
| |
| Increased Register Requirements | |
| |
| |
| |
| Previous Work | |
| |
| |
| |
| A Motivating Example for Prefetching Loads | |
| |
| |
| |
| Prefetching Loads | |
| |
| |
| |
| Compiler Support for Identifying Candidates for Prefetching Loads | |
| |
| |
| |
| Cache Design | |
| |
| |
| |
| Experiment | |
| |
| |
| |
| Initiation Interval | |
| |
| |
| |
| Performance | |
| |
| |
| |
| Register Pressure | |
| |
| |
| |
| Conclusion | |
| |
| |
| |
| Register Allocation for Embedded System | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Java exception and local variable consistency problem | |
| |
| |
| |
| Partially fixed register allocation algorithm | |
| |
| |
| |
| Experimental result | |
| |
| |
| |
| Summary | |
| |
| |
| |
| Is Compiling for Performance == Compiling for Power? | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Related Work | |
| |
| |
| |
| Motivating Examples | |
| |
| |
| |
| Compiler Optimizations | |
| |
| |
| |
| Standard Optimization Levels | |
| |
| |
| |
| Individual Optimizations | |
| |
| |
| |
| Experimental Results | |
| |
| |
| |
| Wattch 1.0 and Benchmarks | |
| |
| |
| |
| Results | |
| |
| |
| |
| Influence of Standard Optimizations on Energy | |
| |
| |
| |
| Influence of Standard Optimizations on Power | |
| |
| |
| |
| Influence of Individual Optimizations on Energy and Power | |
| |
| |
| |
| Conclusions | |
| |
| |
| |
| A Technology-Scalable Architecture for Fast Clocks and High ILP | |
| |
| |
| |
| |
| Introduction | |
| |
| |
| |
| Architecture | |
| |
| |
| |
| Computation Nodes | |
| |
| |
| |
| Execution Model | |
| |
| |
| |
| Instruction Mapping | |
| |
| |
| |
| Instruction Wakeup and Execution | |
| |
| |
| |
| Block Mapping | |
| |
| |
| |
| Instruction Encoding | |
| |
| |
| |
| Role of the Compiler | |
| |
| |
| |
| Preliminary Analysis | |
| |
| |
| |
| Instruction Behavior | |
| |
| |
| |
| Block Size | |
| |
| |
| |
| Grid Utilization | |
| |
| |
| |
| Register Behavior | |
| |
| |
| |
| Input, Output and Temporary Data | |
| |
| |
| |
| Register fanout | |
| |
| |
| |
| Technology Evaluation | |
| |
| |
| |
| Related Work | |
| |
| |
| |
| Conclusion | |
| |
| |
| Topic Index | |
| |
| |
| Author Index | |