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Introduction | |
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A Digital Signal-Processing System | |
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Programmable Digital Signal Processors | |
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Major Features of Programmable Digital Signal Processors | |
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The Scope of the Book | |
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References | |
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Introduction to Digital Signal Processing | |
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Introduction | |
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A Digital Signal-Processing System | |
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The Sampling Process | |
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Discrete Time Sequences | |
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Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) | |
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The DFT Pair | |
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The Relationship between DFT and Frequency Response | |
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The Fast Fourier Transform (FFT) | |
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Linear Time-Invariant Systems | |
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Convolution | |
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Z-Transform | |
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The System Function | |
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Digital Filters | |
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Finite Impulse Response (FIR) Filters | |
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Infinite Impulse Response (IIR) Filters | |
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FIR Filter Design | |
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IIR Filter Design | |
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Decimation and Interpolation | |
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Analysis and Design Tool for DSP Systems: MATLAB | |
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Digital Signal Processing Using MATLAB | |
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Summary | |
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References | |
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Assignments | |
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Laboratory Assignment | |
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Computational Accuracy in DSP Implementations | |
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Introduction | |
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Number Formats for Signals and Coefficients in DSP Systems | |
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Fixed-Point Format | |
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Double-Precision Fixed-Point Format | |
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Floating-Point Format | |
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Block Floating-Point Format | |
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Dynamic Range and Precision | |
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Sources of Error in DSP Implementations | |
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A/D Conversion Errors | |
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DSP Computational Errors | |
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D/A Conversion Errors | |
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Compensating Filter | |
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Summary | |
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References | |
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Assignments | |
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Architectures for Programmable Digital Signal-Processing Devices | |
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Introduction | |
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Basic Architectural Features | |
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DSP Computational Building Blocks | |
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Multiplier | |
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Shifter | |
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Multiply and Accumulate (MAC) Unit | |
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Arithmetic and Logic Unit | |
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Bus Architecture and Memory | |
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On-Chip Memory | |
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Organization of the On-Chip Memory | |
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Data Addressing Capabilities | |
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Immediate Addressing Mode | |
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Register Addressing Mode | |
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Direct Addressing Mode | |
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Indirect Addressing Mode | |
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Special Addressing Modes | |
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Address Generation Unit | |
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Programmability and Program Execution | |
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Program Control | |
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Program Sequencer | |
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Speed Issues | |
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Hardware Architecture | |
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Parallelism | |
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Pipelining | |
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System Level Parallelism and Pipelining | |
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Features for External Interfacing | |
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Summary | |
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References | |
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Assignments | |
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Programmable Digital Signal Processors | |
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Introduction | |
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Commercial Digital Signal-Processing Devices | |
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Data Addressing Modes of TMS320C54xx Digital Signal Processors | |
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Bus Structure | |
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Central Processing Unit (CPU) | |
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Internal Memory and Memory-Mapped Registers | |
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Data Addressing Modes of TMS320C54xx Processors | |
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Immediate Addressing | |
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Absolute Addressing | |
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Accumulator Addressing | |
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Direct Addressing | |
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Indirect Addressing | |
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Memory-Mapped Register Addressing | |
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Stack Addressing | |
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Memory Space of TMS320C54xx Processors | |
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Program Control | |
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TMS320C54xx Instructions and Programming | |
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Summary of the Instruction Set of TMS320C54xx Processors | |
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Programming Examples | |
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On-Chip Peripherals | |
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Hardware Timer | |
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Host Port Interface (HPI) | |
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Clock Generator | |
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Serial I/O Ports | |
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Interrupts of TMS320C54xx Processors | |
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Pipeline Operation of TMS320C54xx Processors | |
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Summary | |
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References | |
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Assignments | |
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Development Tools for Digital Signal-Processing Implementations | |
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Introduction | |
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The DSP Development Tools | |
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The DSP System Design Kit (DSK) | |
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Software for Development | |
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The Assembler and the Assembly Source File | |
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The Linker and Memory Allocation | |
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The C/C[superscript ++] Compiler | |
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The Code Composer Studio (CCS) | |
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Building a Project | |
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The Debug Options | |
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DSP Software Development Example | |
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Summary | |
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References | |
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Laboratory Assignments | |
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Implementations of Basic DSP Algorithms | |
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Introduction | |
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The Q-notation | |
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FIR Filters | |
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IIR Filters | |
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Interpolation Filters | |
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Decimation Filters | |
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PID Controller | |
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Adaptive Filters | |
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2-D Signal Processing | |
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Matrix Multiplication | |
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Summary | |
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References | |
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Assignments | |
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Implementation of FFT Algorithms | |
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Introduction | |
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An FFT Algorithm for DFT Computation | |
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2-Point DFT Computation | |
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4-Point DFT Computation | |
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8-Point DFT Computation | |
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N = 2[superscript M]-Point Computation | |
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A Butterfly Computation | |
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Overflow and Scaling | |
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Bit-Reversed Index Generation | |
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An 8-Point FFT Implementation on the TMS320C54xx | |
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Computation of the Signal Spectrum | |
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Summary | |
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References | |
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Assignments | |
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Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices | |
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Introduction | |
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Memory Space Organization | |
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External Bus Interfacing Signals | |
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Memory Interface | |
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Timing Sequence for External Memory Access | |
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Wait States | |
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Memory Design Examples | |
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Parallel I/O Interface | |
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Programmed I/O | |
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Interrupts and I/O | |
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Handling of Interrupts | |
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Direct Memory Access (DMA) | |
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DMA Operation Configuration | |
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Register Subaddressing | |
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Summary | |
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References | |
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Assignments | |
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Interfacing Serial Converters to a Programmable DSP Device | |
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Introduction | |
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Synchronous Serial Interface | |
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A Multichannel Buffered Serial Port (McBSP) | |
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McBSP Programming | |
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A CODEC Interface Circuit | |
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CODEC Programming | |
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A CODEC-DSP Interface Example | |
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Summary | |
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References | |
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Assignments | |
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Applications of Programmable DSP Devices | |
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Introduction | |
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A DSP System | |
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DSP-Based Biotelemetry Receiver | |
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Pulse Position Modulation (PPM) | |
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Decoding Scheme for the PPM Receiver | |
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Biotelemetry Receiver Implementation | |
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ECG Signal Processing for Heart Rate Determination | |
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A Speech Processing System | |
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A Digital Model for Production of Speech Signal | |
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Autocorrelation | |
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Implementation on the TMS320C54xx Processor | |
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An Image Processing System | |
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JPEG Algorithm Overview | |
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JPEG Encoding | |
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JPEG Decoding | |
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Encoding and Decoding of JPEG Using the TMS320C54xx | |
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A Position Control System for a Hard Disk Drive | |
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DSP-Based Power Meter | |
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Power Measurement System | |
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Software for the Power Meter | |
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Summary | |
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References | |