Designer's Guide to Asynchronous VLSI

Name: Designer's Guide to Asynchronous VLSI
Price: 163.43 USD
Availability: InStock
ISBN: 9780521872447

ISBN-10: 0521872448

ISBN-13: 9780521872447

Edition: 2010

Authors: Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti

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Book details

List price: $229.95
Copyright year: 2010
Publisher: Cambridge University Press
Publication date: 2/4/2010
Binding: Hardcover
Pages: 352
Size: 7.09" wide x 10.00" long x 0.83" tall
Weight: 1.848
Language: English

Recep O. Ozdag is IC Design Manager at Fulcrum Microsystems and a part-time Lecturer at USC, where he received his Ph.D. in 2004. He is a recipient of the British Chevening Scholarship, the Turkish Ministry of Education Post-Graduate Scholarship and the Turkish Higher Education Council Scholarship.

Marcos Ferretti Co-Founded PST Electronica, Brazil - an automotive electronic systems manufacturing company - where he is currently Engineering Director and Vice President. He received his Ph.D. from USC in 2004 and was co-recipient of the USC Electrical Engineering-Systems Best Paper Award in the same year.



Acknowledgments



Introduction



Synchronous design basics



Challenges in synchronous design



Asynchronous design basics



Asynchronous design flows



Potential advantages of asynchronous design



Challenges in asynchronous design



Organization of the book



Channel-based asynchronous design



Asynchronous channels



Sequencing and concurrency



Asynchronous memories and holding state



Arbiters



Design examples



Exercises



Modeling channel-based designs



Communicating sequential processes



Using asynchronous-specific languages



Using software programming languages



Using existing hardware design languages



Modeling channel communication in Verilog



Implementing VerilogCSP macros



Debugging in VerilogCSP



Summary of VerilogCSP macros



Exercises



Pipeline performance



Block metrics



Linear pipelines



Pipeline loops



Forks and joins



More complex pipelines



Exercises



Performance analysis and optimization



Petri nets



Modeling pipelines using channel nets



Performance analysis



Performance optimization



Advanced topic: stochastic performance analysis



Exercises



Deadlock



Deadlock caused by incorrect circuit design



Deadlock caused by architectural token mismatch



Deadlock caused by arbitration



A taxonomy of design styles



Delay models



Timing constraints



Input-output mode versus fundamental mode



Logic styles



Datapath design



Design flows: an overview of approaches



Exercises



Synthesis-based controller design



Fundamental-mode Huffman circuits



STG-based design



Exercises



Micropipeline design



Two-phase micropipelines



Four-phase micropipelines



True-four-phase pipelines



Delay line design



Other micropipeline techniques



Exercises



Syntax-directed translation



Tangram



Handshake components



Translation algorithm



Control component implementation



Datapath component implementations



Peephole optimizations



Self-initialization



Testability



Design examples



Summary



Exercises



Quasi-delay-insensitive pipeline templates



Weak-conditioned half buffer



Precharged half buffer



Precharged full buffer



Why input-completion sensing?



Reduced-stack precharged half buffer (RSPCHB)



Reduced-stack precharged full buffer (RSPCFB)



Quantitative comparisons



Token insertion



Arbiter



Exercises



Timed pipeline templates



Williams' PS0 pipeline



Lookahead pipelines overview



Dual-rail lookahead pipelines



Single-rail lookahead pipelines



High-capacity pipelines (single-rail)



Designing non-linear pipeline structures



Lookahead pipelines (single-rail)



Lookahead pipelines (dual-rail)



High-capacity pipelines (single-rail)



Conditionals



Loops



Simulation results



Summary



Single-track pipeline templates



Introduction



GasP bundled data



Pulsed logic



Single-track full-buffer template



STFB pipeline stages



STFB standard-cell implementation



Back-end design flow and library development



The evaluation and demonstration chip



Conclusions and open questions



Exercises



Asynchronous crossbar



Fulcrum's Nexus asynchronous crossbar



Clock domain converter



Design example: the Fano algorithm



The Fano algorithm



The asynchronous Fano algorithm



An asynchronous semi-custom physical design flow


Index