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| Preface | |
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| Introduction | |
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| A Quick View of Technological Advances | |
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| Performance Metrics | |
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| Performance Evaluation | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| References | |
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| The Basics | |
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| Pipelining | |
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| Caches | |
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| Virtual Memory and Paging | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| References | |
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| Superscalar Processors | |
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| From Scalar to Superscalar Processors | |
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| Overview of the Instruction Pipeline of the DEC Alpha 21164 | |
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| Introducing Register Renaming, Reorder Buffer, and Reservation Stations | |
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| Overview of the Pentium P6 Microarchitecture | |
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| VLIW/EPIC Processors | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| References | |
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| Front-End: Branch Prediction, Instruction Fetching, and Register Renaming | |
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| Branch Prediction | |
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| Sidebar: The DEC Alpha 21264 Branch Predictor | |
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| Instruction Fetching | |
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| Decoding | |
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| Register Renaming (a Second Look) | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| Programming Projects | |
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| References | |
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| Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters | |
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| Instruction Issue and Scheduling (Wakeup and Select) | |
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| Memory-Accessing Instructions | |
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| Back-End Optimizations | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| Programming Project | |
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| References | |
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| The Cache Hierarchy | |
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| Improving Access to L1 Caches | |
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| Hiding Memory Latencies | |
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| Design Issues for Large Higher-Level Caches | |
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| Main Memory | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| Programming Projects | |
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| References | |
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| Multiprocessors | |
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| Multiprocessor Organization | |
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| Cache Coherence | |
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| Synchronization | |
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| Relaxed Memory Models | |
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| Multimedia Instruction Set Extensions | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| References | |
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| Multithreading and (Chip) Multiprocessing | |
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| Single-Processor Multithreading | |
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| General-Purpose Multithreaded Chip Multiprocessors | |
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| Special-Purpose Multithreaded Chip Multiprocessors | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| Exercises | |
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| References | |
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| Current Limitations and Future Challenges | |
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| Power and Thermal Management | |
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| Technological Limitations: Wire Delays and Pipeline Depths | |
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| Challenges for Chip Multiprocessors | |
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| Summary | |
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| Further Reading and Bibliographical Notes | |
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| References | |
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| Bibliography | |
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| Index | |