Design Through Verilog HDL

Name: Design Through Verilog HDL
Price: 71.94 USD
Availability: InStock
ISBN: 9780471441489

ISBN-10: 0471441481

ISBN-13: 9780471441489

Edition: 2004

Authors: T. R. Padmanabhan, B. Bala Tripura Sundari

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Book details

List price: $171.95
Copyright year: 2004
Publisher: John Wiley & Sons, Incorporated
Publication date: 11/5/2003
Binding: Hardcover
Pages: 472
Size: 6.36" wide x 9.51" long x 1.09" tall
Weight: 1.760
Language: English



Preface


Acknowledgements



Introduction to Vlsi Design



Introduction



Conventional Approach to Digital Design



Vlsi Design



Asic Design Flow



Role of Hdl



Introduction to Verilog



Verilog as an Hdl



Levels of Design Description



Concurrency



Simulation and Synthesis



Functional Verification



System Tasks



Programming Language Interface (PLI)



Module



Simulation and Synthesis Tools



Test Benches



Language Constructs and Conventions in Verilog



Introduction



Keywords



Identifiers



White Space Characters



Comments



Numbers



Strings



Logic Values



Strengths



Data Types



Scalars and Vectors



Parameters



Memory



Operators



System Tasks



Exercises



Gate Level Modeling-1



Introduction



And Gate Primitive



Module Structure



Other Gate Primitives



Illustrative Examples



Tri-State Gates



Array of Instances of Primitives



Additional Examples



Exercises



Gate Level Modeling-2



Introduction



Design of Flip-Flops with Gate Primitives



Delays



Strengths and Contention Resolution



Net Types



Design of Basic Circuits



Exercises



Modeling at Data Flow Level



Introduction



Continuous Assignment Structures



Delays and Continuous Assignments



Assignment to vectors



Operators



Additional Examples



Exercises



Behavioral Modeling



Introduction



Operations and Assignments



Functional Bifurcation



Initial Construct



Always Construct



Examples



Assignments with Delays



Wait Construct



Multiple Always Blocks



Designs at Behavioral Level



Blocking and Nonblocking Assignments



The case Statement



Simulation Flow



Exercises



Behavioral Modeling II



Introduction



If and if-else Constructs



Assign-deassign Construct



Repeat Construct



For Loop



The disable Construct



While Loop



Forever Loop



Parallel Blocks



Force-release Construct



Event



Exercises



Functions, Tasks, and User-Defined Primitives



Introductiuon



Function



Tasks



User-Defined Primitives (UDP)



Exercises



Switch Level Modeling



Introduction



Basic Transistor Switches



Cmos Switch



Bidirectional Gates



Time Delays with Switch Primitives



Instantiations with Strengths and Delays



Strength Contention with Trireg Nets



Exercises



System Tasks, Functions, and Compiler Directives



Introduction



Parameters



Path Delays



Module Parameters



System Tasks and Functions



File-Based Tasks and Functions



Compiler Directives



Hierarchical Access



General Observations



Exercises



Queues, Plas, and Fsms



Introduction



Queues



Programmable Logic Devices (PLDs)



Design of Finite State Machines



Exercises



Keywords and Their Significance



Truth Tables of Gates and Switches


References


Index