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| Preface | |
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| Purpose | |
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| Coverage | |
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| How to Use This Book | |
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| Laboratory | |
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| Additional Materials | |
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| Acknowledgments | |
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| About the Authors | |
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| Introduction | |
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| Embedded Systems Overview | |
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| Design Challenge--Optimizing Design Metrics | |
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| Common Design Metrics | |
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| The Time-to-Market Design Metric | |
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| The NRE and Unit Cost Design Metrics | |
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| The Performance Design Metric | |
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| Processor Technology | |
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| General-Purpose Processors--Software | |
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| Single-Purpose Processors--Hardware | |
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| Application-Specific Processors | |
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| IC Technology | |
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| Full-Custom/VLSI | |
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| Semicustom ASIC (Gate Array and Standard Cell) | |
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| PLD | |
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| Trends | |
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| Design Technology | |
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| Compilation/Synthesis | |
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| Libraries/IP | |
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| Test/Verification | |
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| More Productivity Improvers | |
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| Trends | |
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| Trade-offs | |
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| Design Productivity Gap | |
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| Summary and Book Outline | |
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| References and Further Reading | |
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| Exercises | |
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| Custom Single-Purpose Processors: Hardware | |
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| Introduction | |
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| Combinational Logic | |
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| Transistors and Logic Gates | |
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| Basic Combinational Logic Design | |
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| RT-Level Combinational Components | |
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| Sequential Logic | |
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| Flip-Flops | |
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| RT-Level Sequential Components | |
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| Sequential Logic Design | |
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| Custom Single-Purpose Processor Design | |
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| RT-Level Custom Single-Purpose Processor Design | |
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| Optimizing Custom Single-Purpose Processors | |
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| Optimizing the Original Program | |
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| Optimizing the FSMD | |
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| Optimizing the Datapath | |
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| Optimizing the FSM | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| General-Purpose Processors: Software | |
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| Introduction | |
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| Basic Architecture | |
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| Datapath | |
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| Control Unit | |
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| Memory | |
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| Operation | |
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| Instruction Execution | |
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| Pipelining | |
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| Superscalar and VLIW Architectures | |
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| Programmer's View | |
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| Instruction Set | |
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| Program and Data Memory Space | |
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| Registers | |
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| I/O | |
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| Interrupts | |
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| Example: Assembly-Language Programming of Device Drivers | |
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| Operating System | |
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| Development Environment | |
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| Design Flow and Tools | |
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| Example: Instruction-Set Simulator for a Simple Processor | |
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| Testing and Debugging | |
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| Application-Specific Instruction-Set Processors (ASIPs) | |
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| Microcontrollers | |
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| Digital Signal Processors (DSP) | |
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| Less-General ASIP Environments | |
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| Selecting a Microprocessor | |
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| General-Purpose Processor Design | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Standard Single-Purpose Processors: Peripherals | |
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| Introduction | |
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| Timers, Counters, and Watchdog Timers | |
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| Timers and Counters | |
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| Example: Reaction Timer | |
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| Watchdog Timers | |
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| Example: ATM Timeout Using a Watchdog Timer | |
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| UART | |
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| Pulse Width Modulators | |
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| Overview | |
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| Example: Controlling a DC Motor Using a PWM | |
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| LCD Controllers | |
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| Overview | |
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| Example: LCD Initialization | |
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| Keypad Controllers | |
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| Stepper Motor Controllers | |
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| Overview | |
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| Example: Using a Stepper Motor Driver | |
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| Example: Controlling a Stepper Motor Directly | |
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| Analog-to-Digital Converters | |
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| Example: Successive Approximation | |
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| Real-Time Clocks | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Memory | |
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| Introduction | |
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| Memory Write Ability and Storage Permanence | |
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| Write Ability | |
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| Storage Permanence | |
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| Trade-offs | |
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| Common Memory Types | |
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| Introduction to "Read-Only" Memory--ROM | |
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| Mask-Programmed ROM | |
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| OTP ROM--One-Time Programmable ROM | |
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| EPROM--Erasable Programmable ROM | |
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| EEPROM--Electrically Erasable Programmable ROM | |
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| Flash Memory | |
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| Introduction to Read-Write Memory--RAM | |
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| SRAM--Static RAM | |
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| DRAM--Dynamic RAM | |
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| PSRAM--Pseudo-Static RAM | |
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| NVRAM--Nonvolatile RAM | |
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| Example: HM6264 and 27C256 RAM/ROM Devices | |
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| Example: TC55V2325FF-100 Memory Device | |
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| Composing Memory | |
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| Memory Hierarchy and Cache | |
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| Cache Mapping Techniques | |
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| Cache-Replacement Policy | |
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| Cache Write Techniques | |
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| Cache Impact on System Performance | |
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| Advanced RAM | |
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| The Basic DRAM | |
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| Fast Page Mode DRAM (FPM DRAM) | |
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| Extended Data Out DRAM (EDO DRAM) | |
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| Synchronous (S) and Enhanced Synchronous (ES) DRAM | |
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| Rambus DRAM (RDRAM) | |
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| DRAM Integration Problem | |
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| Memory Management Unit (MMU) | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Interfacing | |
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| Introduction | |
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| Communication Basics | |
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| Basic Terminology | |
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| Basic Protocol Concepts | |
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| Example: The ISA Bus Protocol--Memory Access | |
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| Microprocessor Interfacing: I/O Addressing | |
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| Port and Bus-Based I/O | |
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| Memory-Mapped I/O and Standard I/O | |
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| Example: The ISA Bus Protocol--Standard I/O | |
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| Example: A Basic Memory Protocol | |
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| Example: A Complex Memory Protocol | |
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| Microprocessor Interfacing: Interrupts | |
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| Microprocessor Interfacing: Direct Memory Access | |
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| Example: DMA I/O and the ISA Bus Protocol | |
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| Arbitration | |
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| Priority Arbiter | |
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| Daisy-Chain Arbitration | |
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| Network-Oriented Arbitration Methods | |
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| Example: Vectored Interrupt Using an Interrupt table | |
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| Multilevel Bus Architectures | |
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| Advanced Communication Principles | |
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| Parallel Communication | |
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| Serial Communication | |
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| Wireless Communication | |
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| Layering | |
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| Error Detection and Correction | |
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| Serial Protocols | |
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| I[superscript 2]C | |
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| CAN | |
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| FireWire | |
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| USB | |
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| Parallel Protocols | |
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| PCI Bus | |
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| ARM Bus | |
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| Wireless Protocols | |
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| IrDA | |
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| Bluetooth | |
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| IEEE 802.11 | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Digital Camera Example | |
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| Introduction | |
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| Introduction to a Simple Digital Camera | |
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| User's Perspective | |
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| Designer's Perspective | |
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| Requirements Specification | |
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| Nonfunctional Requirements | |
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| Informal Functional Specification | |
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| Refined Functional Specification | |
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| Design | |
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| Microcontroller Alone | |
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| Microcontroller and CCDPP | |
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| Microcontroller and CCDPP/Fixed-Point DCT | |
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| Microcontroller and CCDPP/DCT | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| State Machine and Concurrent Process Models | |
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| Introduction | |
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| Models vs. Languages, Text vs. Graphics | |
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| Models vs. Languages | |
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| Textual Languages vs. Graphical Languages | |
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| An Introductory Example | |
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| A Basic State Machine Model: Finite-State Machines | |
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| Finite-State Machine with Datapath Model: FSMD | |
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| Using State Machines | |
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| Describing a System as a State Machine | |
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| Comparing State Machine and Sequential Program Models | |
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| Capturing State Machines in Sequential Programming Language | |
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| HCFSM and the Statecharts Language | |
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| Program-State Machine Model (PSM) | |
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| The Role of an Appropriate Model and Language | |
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| Concurrent Process Model | |
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| Concurrent Processes | |
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| Process Create and Terminate | |
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| Process Suspend and Resume | |
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| Process Join | |
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| Communication among Processes | |
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| Shared Memory | |
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| Message Passing | |
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| Synchronization among Processes | |
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| Condition Variables | |
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| Monitors | |
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| Implementation | |
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| Creating and Terminating Processes | |
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| Suspending and Resuming Processes | |
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| Joining a Process | |
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| Scheduling Processes | |
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| Dataflow Model | |
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| Real-Time Systems | |
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| Windows CE | |
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| QNX | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Control Systems | |
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| Introduction | |
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| Open-Loop and Closed-Loop Control Systems | |
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| Overview | |
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| A First Example: An Open-Loop Automobile Cruise Controller | |
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| A Second Example: A Closed-Loop Automobile Cruise Controller | |
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| General Control Systems and PID Controllers | |
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| Control Objectives | |
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| Modeling Real Physical Systems | |
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| Controller Design | |
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| Software Coding of a PID Controller | |
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| PID Tuning | |
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| Practical Issues Related to Computer-Based Control | |
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| Quantization and Overflow Effects | |
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| Aliasing | |
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| Computation Delay | |
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| Benefits of Computer-Based Control Implementations | |
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| Repeatability, Reproducability, and Stability | |
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| Programmability | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| IC Technology | |
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| Introduction | |
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| Full-Custom (VLSI) IC Technology | |
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| Semi-Custom (ASIC) IC Technology | |
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| Gate Array Semi-Custom IC Technology | |
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| Standard Cell Semi-Custom IC Technology | |
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| Programmable Logic Device (PLD) IC Technology | |
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| Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Design Technology | |
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| Introduction | |
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| Automation: Synthesis | |
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| "Going up": The Parallel Evolution of Compilation and Synthesis | |
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| Synthesis Levels | |
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| Logic Synthesis | |
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| Register-Transfer Synthesis | |
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| Behavioral Synthesis | |
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| System Synthesis and Hardware/Software Codesign | |
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| Temporal and Spatial Thinking | |
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| Verification: Hardware/Software Co-Simulation | |
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| Formal Verification and Simulation | |
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| Simulation Speed | |
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| Hardware-Software Co-Simulation | |
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| Emulators | |
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| Reuse: Intellectual Property Cores | |
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| Hard, soft and firm cores | |
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| New Challenges Posed by Cores to Processor Providers | |
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| New Challenges Posed by Cores to Processor Users | |
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| Design Process Models | |
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| Summary | |
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| Book Summary | |
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| References and Further Reading | |
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| Exercises | |
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| Online Resources | |
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| Introduction | |
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| Summary of the ESD Web Page | |
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| Lab Resources | |
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| About the Book Cover | |
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| Outdoors | |
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| Indoors | |
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| Index | |