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CMOS Mixed-Signal Circuit Design

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ISBN-10: 0471227544

ISBN-13: 9780471227540

Edition: 2002

Authors: R. Jacob Baker

List price: $100.95
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Following the success of 'CMOS: Circuit Design, Layout and Simulation', this book continues the discussion of design techniques in CMOS.
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Book details

List price: $100.95
Copyright year: 2002
Publisher: John Wiley & Sons, Incorporated
Publication date: 6/17/2002
Binding: Hardcover
Pages: 520
Size: 6.75" wide x 9.75" long x 1.25" tall
Weight: 1.980
Language: English

Preface to Volume II
Data Converter Modeling
Sampling and Aliasing: A Modeling Approach
Impulse Sampling
A Note Concerning the AAF and RCF
Time-Domain Description of Reconstruction
Using SPICE for Spectral Analysis (Looking at the Spectrum of a Signal)
Representing the Impulse Sampler's Output in the Z-Domain
An Important Note
The Sample and Hold
SPICE Modeling the Sample and Hold
S/H Spectral Response
Circuit Concerns for Implementing the S/H
SPICE Models for DACs and ADCs
The Ideal DAC
SPICE Modeling Approach
The Ideal ADC
Quantization Noise
Viewing the Quantization Noise Spectrum Using Simulations
An Important Note
RMS Quantization Noise Voltage
Treating Quantization Noise as a Random Variable
Calculating RMS Quantization Noise Voltage from a Spectrum
The DFT's Relationship to the Continuous Time Fourier Transform
Quantization Noise Voltage Spectral Density
Reducing Quantization Noise Using Averaging
The Noise Spectral Density View of Averaging
An Important Note
Practical Implementation of Averaging in ADCs
Data Converter SNR
Data Converter SNR: An Overview
Effective Number of Bits
Signal-to-Noise Plus Distortion Ratio
Spurious-Free Dynamic Range
Dynamic Range
Specifying SNR and SNDR
Clock Jitter
Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements
A Practical Note
Modeling Clock Jitter with SPICE
Using Our SPICE Jitter Model
A Tool: The Spectral Density
The Spectral Density of Deterministic Signals: An Overview
The Spectral Density of Random Signals: An Overview
Specifying Phase Noise from Measured Data
Improving SNR Using Averaging
Using Averaging to Improve SNR
Spectral Density View of Averaging Revisited
An Important Observation
Jitter and Averaging
Relaxed Requirements Placed on the Antialiasing Filter
Data Converter Linearity Requirements
Adding a Noise Dither to the ADC Input
The Z-Plane
Decimating Filters for ADCs
The Accumulate and Dump
Averaging without Decimation
Relaxed Requirements Placed on the Antialiasing Filter Revisited
Implementing Averaging Filters
Aliasing Concerns When Using Decimation
A Note Concerning Stability
Decimating Down to 2B
Interpolating Filters for DACs
The Dump and Interpolate
Practical Implementation of Interpolators
Bandpass and Highpass Sinc Filters
Canceling Zeroes to Create Highpass and Bandpass Filters
Frequency Sampling Filters
Using Feedback to Improve SNR
The Discrete Analog Integrator
A Note Concerning Block Diagrams
Noise-Shaping Data Converters
Noise-Shaping Fundamentals
SPICE Models
Nonoverlapping Clock Generation and Switches
Op-Amp Modeling
SPICE Modeling a 1-Bit ADC
First-Order Noise-Shaping
A Digital First-Order NS Demodulator
Modulation Noise in First-Order NS Modulators
RMS Quantization Noise in a First-Order Modulator
Decimating and Filtering the Output of a NS Modulator
Implementing the Sinc Averaging Filter Revisited
Analog Sinc Averaging Filters using SPICE
Using our SPICE Sinc Filter Model
Analog Implementation of the First-Order NS Modulator
The Feedback DAC
Understanding Averaging and the Use of Digital Filtering with the Modulator
Pattern Noise from DC Inputs (Limit Cycle Oscillations)
Integrator and Forward Modulator Gain
Comparator Gain, Offset, Noise, and Hysteresis
Op-Amp Gain (Integrator Leakage)
Op-Amp Settling Time
Op-Amp Offset
Op-Amp Input Referred Noise
Practical Implementation of the First-Order NS Modulator
Fully-Differential Modulator with a Single-Ended Input
Second-Order Noise-Shaping
Second-Order Modulator Topology
Integrator Gain
Implementing Feedback Gains in the DAI
Using Two Delaying Integrators to Implement the Second-Order Modulator
Selecting Modulator (Integrator) Gains
Understanding Modulator SNR
Noise-Shaping Topologies
Higher-Order Modulators
M-Order Modulator Topology
Decimating the Output of an M-Order NS Modulator
Implementing Higher-Order, Single-Stage, Modulators
Multibit Modulators
Simulating a Multibit NS Modulator Using SPICE
Multibit Demodulator (Used in a NS DAC) Implementation (Error Feedback)
Implementation Concerns
Cascaded Modulators
Second-Order (1-1) Modulators
Third-Order (1-1-1) Modulators
Third-Order (2-1) Modulators
Implementing the Additional Summing Input
Bandpass Modulators
Implementing a Bandpass Modulator
Submicron CMOS Circuit Design
Submicron CMOS: Overview and Models
CMOS Process Flow
Capacitors and Resistors
Using a MOSFET as a Capacitor
Using a Native or Natural MOSFET Capacitor
The Floating MOS Capacitor
Metal Capacitors
An Important Note
Model Selection
Model Parameters
An Important Note
A Note Concerning "Long L MOSFETs"
Digital Circuit Design
The MOSFET Switch
Bidirectional Switches
A Clocked Comparator
Common-Mode Noise Elimination
Delay Elements
An Adder
Analog Circuit Design
Selecting the Excess Gate Voltage
Selecting the Channel Length
Small-Signal Transconductance, g[subscript m]
MOSFET Transition Frequency, f[subscript T]
The Beta Multiplier Self-Biased Reference
Op-Amp Design
Output Swing
Slew-rate Concerns
Differential Output Op-Amp
Circuit Noise
Thermal Noise
The Spectral Characteristics of Thermal Noise
Noise Equivalent Bandwidth
Noise Performance of the Source-Follower
Noise Performance of a Cascade of Amplifiers
DAI Noise Performance
Implementing Data Converters
R-2R Topologies for DACs
The Current-Mode R-2R DAC
The Voltage-Mode R-2R DAC
A Wide-Swing Current-Mode R-2R DAC
DNL Analysis
INL Analysis
Experimental Results
Improving DNL (Segmentation)
Trimming DAC Offset
Trimming DAC Gain
Improving INL by Calibration
Topologies Without an Op-Amp
The Voltage-Mode DAC
Two Important Notes Concerning Glitches
The Current-Mode (Current Steering) DAC
Op-Amps in Data Converters
Gain Bandwidth Product of the Noninverting Op-Amp Topology
Gain Bandwidth Product of the Inverting Op-Amp Topology
Op-Amp Gain
Op-Amp Unity Gain Frequency
Op-Amp Offset
Adding an Auxiliary Input Port
Implementing ADCs
Implementing the S/H
A Single-Ended to Differential Output S/H
The Cyclic ADC
Comparator Placement
Implementing Subtraction in the S/H
Understanding Output Swing
The Pipeline ADC
Using 1.5 Bits/Stage
Capacitor Error Averaging
Comparator Placement
Clock Generation
Offsets and Alternative Design Topologies
Dynamic CMFB
Layout of Pipelined ADCs
Integrator-Based CMOS Filters
Integrator Building Blocks
Lowpass Filters
Active-RC Integrators
Effects of Finite Op-Amp Gain Bandwidth Product
Active-RC SNR
MOSFET-C Integrators
Why use an Active Circuit (an Op-Amp)
g[subscript m]-C (Transconductor-C) Integrators
Common-Mode Feedback Considerations
A High-Frequency Transconductor
Discrete-Time Integrators
An Important Note
Exact Frequency Response of a First-Order Discrete- Time Digital (or Ideal SC) Filter
Filtering Topologies
The Bilinear Transfer Function
Active-RC Implementation
Transconductor-C Implementation
Switched-Capacitor Implementation
Digital Filter Implementation
The Canonic Form (or Standard Form) of a Digital Filter
The Biquadratic Transfer Function
Active-RC Implementation
Switched-Capacitor Implementation
High Q
Q Peaking and Instability
Transconductor-C Implementation
The Digital Biquad
Filters using Noise-Shaping
Removing Modulation Noise
Implementing the Multipliers
At the Bench
A Push-Pull Amplifier
Deadbug Prototyping
Testing the Circuit
A First-Order Noise-Shaping Modulator
Prototyping the Modulator
Measuring 1/f Noise
Input-Referred Noise Voltage
Chopper Stabilization
A Discrete Analog Integrator
Clock Generation
Prototyping the Filter
Quantization Noise
Prototyping the ADC Circuit
About the Author