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| Preface to Volume II | |
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| Data Converter Modeling | |
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| Sampling and Aliasing: A Modeling Approach | |
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| Impulse Sampling | |
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| A Note Concerning the AAF and RCF | |
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| Time-Domain Description of Reconstruction | |
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| Using SPICE for Spectral Analysis (Looking at the Spectrum of a Signal) | |
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| Representing the Impulse Sampler's Output in the Z-Domain | |
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| An Important Note | |
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| The Sample and Hold | |
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| SPICE Modeling the Sample and Hold | |
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| S/H Spectral Response | |
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| Circuit Concerns for Implementing the S/H | |
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| SPICE Models for DACs and ADCs | |
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| The Ideal DAC | |
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| SPICE Modeling Approach | |
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| The Ideal ADC | |
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| Summary | |
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| Quantization Noise | |
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| Viewing the Quantization Noise Spectrum Using Simulations | |
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| An Important Note | |
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| RMS Quantization Noise Voltage | |
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| Treating Quantization Noise as a Random Variable | |
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| Calculating RMS Quantization Noise Voltage from a Spectrum | |
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| The DFT's Relationship to the Continuous Time Fourier Transform | |
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| Quantization Noise Voltage Spectral Density | |
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| Reducing Quantization Noise Using Averaging | |
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| The Noise Spectral Density View of Averaging | |
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| An Important Note | |
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| Practical Implementation of Averaging in ADCs | |
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| Data Converter SNR | |
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| Data Converter SNR: An Overview | |
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| Effective Number of Bits | |
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| Signal-to-Noise Plus Distortion Ratio | |
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| Spurious-Free Dynamic Range | |
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| Dynamic Range | |
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| Specifying SNR and SNDR | |
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| Clock Jitter | |
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| Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements | |
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| A Practical Note | |
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| Modeling Clock Jitter with SPICE | |
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| Using Our SPICE Jitter Model | |
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| A Tool: The Spectral Density | |
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| The Spectral Density of Deterministic Signals: An Overview | |
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| The Spectral Density of Random Signals: An Overview | |
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| Specifying Phase Noise from Measured Data | |
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| Improving SNR Using Averaging | |
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| Using Averaging to Improve SNR | |
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| Spectral Density View of Averaging Revisited | |
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| An Important Observation | |
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| Jitter and Averaging | |
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| Relaxed Requirements Placed on the Antialiasing Filter | |
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| Data Converter Linearity Requirements | |
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| Adding a Noise Dither to the ADC Input | |
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| The Z-Plane | |
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| Decimating Filters for ADCs | |
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| The Accumulate and Dump | |
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| Averaging without Decimation | |
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| Relaxed Requirements Placed on the Antialiasing Filter Revisited | |
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| Implementing Averaging Filters | |
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| Aliasing Concerns When Using Decimation | |
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| A Note Concerning Stability | |
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| Decimating Down to 2B | |
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| Interpolating Filters for DACs | |
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| The Dump and Interpolate | |
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| Practical Implementation of Interpolators | |
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| Bandpass and Highpass Sinc Filters | |
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| Canceling Zeroes to Create Highpass and Bandpass Filters | |
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| Frequency Sampling Filters | |
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| Using Feedback to Improve SNR | |
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| The Discrete Analog Integrator | |
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| A Note Concerning Block Diagrams | |
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| Modulators | |
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| Noise-Shaping Data Converters | |
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| Noise-Shaping Fundamentals | |
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| SPICE Models | |
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| Nonoverlapping Clock Generation and Switches | |
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| Op-Amp Modeling | |
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| SPICE Modeling a 1-Bit ADC | |
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| First-Order Noise-Shaping | |
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| A Digital First-Order NS Demodulator | |
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| Modulation Noise in First-Order NS Modulators | |
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| RMS Quantization Noise in a First-Order Modulator | |
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| Decimating and Filtering the Output of a NS Modulator | |
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| Implementing the Sinc Averaging Filter Revisited | |
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| Analog Sinc Averaging Filters using SPICE | |
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| Using our SPICE Sinc Filter Model | |
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| Analog Implementation of the First-Order NS Modulator | |
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| The Feedback DAC | |
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| Understanding Averaging and the Use of Digital Filtering with the Modulator | |
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| Pattern Noise from DC Inputs (Limit Cycle Oscillations) | |
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| Integrator and Forward Modulator Gain | |
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| Comparator Gain, Offset, Noise, and Hysteresis | |
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| Op-Amp Gain (Integrator Leakage) | |
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| Op-Amp Settling Time | |
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| Op-Amp Offset | |
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| Op-Amp Input Referred Noise | |
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| Practical Implementation of the First-Order NS Modulator | |
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| Fully-Differential Modulator with a Single-Ended Input | |
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| Second-Order Noise-Shaping | |
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| Second-Order Modulator Topology | |
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| Integrator Gain | |
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| Implementing Feedback Gains in the DAI | |
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| Using Two Delaying Integrators to Implement the Second-Order Modulator | |
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| Selecting Modulator (Integrator) Gains | |
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| Understanding Modulator SNR | |
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| Noise-Shaping Topologies | |
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| Higher-Order Modulators | |
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| M-Order Modulator Topology | |
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| Decimating the Output of an M-Order NS Modulator | |
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| Implementing Higher-Order, Single-Stage, Modulators | |
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| Multibit Modulators | |
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| Simulating a Multibit NS Modulator Using SPICE | |
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| Multibit Demodulator (Used in a NS DAC) Implementation (Error Feedback) | |
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| Implementation Concerns | |
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| Cascaded Modulators | |
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| Second-Order (1-1) Modulators | |
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| Third-Order (1-1-1) Modulators | |
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| Third-Order (2-1) Modulators | |
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| Implementing the Additional Summing Input | |
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| Bandpass Modulators | |
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| Implementing a Bandpass Modulator | |
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| Submicron CMOS Circuit Design | |
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| Submicron CMOS: Overview and Models | |
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| CMOS Process Flow | |
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| Capacitors and Resistors | |
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| Using a MOSFET as a Capacitor | |
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| Using a Native or Natural MOSFET Capacitor | |
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| The Floating MOS Capacitor | |
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| Metal Capacitors | |
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| An Important Note | |
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| Resistors | |
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| SPICE MOSFET Modeling | |
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| Model Selection | |
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| Model Parameters | |
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| An Important Note | |
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| A Note Concerning "Long L MOSFETs" | |
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| Digital Circuit Design | |
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| The MOSFET Switch | |
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| Bidirectional Switches | |
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| A Clocked Comparator | |
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| Common-Mode Noise Elimination | |
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| Delay Elements | |
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| An Adder | |
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| Analog Circuit Design | |
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| Biasing | |
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| Selecting the Excess Gate Voltage | |
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| Selecting the Channel Length | |
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| Small-Signal Transconductance, g[subscript m] | |
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| MOSFET Transition Frequency, f[subscript T] | |
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| The Beta Multiplier Self-Biased Reference | |
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| Op-Amp Design | |
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| Output Swing | |
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| Slew-rate Concerns | |
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| Differential Output Op-Amp | |
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| Circuit Noise | |
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| Thermal Noise | |
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| The Spectral Characteristics of Thermal Noise | |
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| Noise Equivalent Bandwidth | |
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| MOSFET Noise | |
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| Noise Performance of the Source-Follower | |
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| Noise Performance of a Cascade of Amplifiers | |
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| DAI Noise Performance | |
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| Implementing Data Converters | |
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| R-2R Topologies for DACs | |
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| The Current-Mode R-2R DAC | |
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| The Voltage-Mode R-2R DAC | |
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| A Wide-Swing Current-Mode R-2R DAC | |
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| DNL Analysis | |
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| INL Analysis | |
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| Switches | |
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| Experimental Results | |
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| Improving DNL (Segmentation) | |
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| Trimming DAC Offset | |
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| Trimming DAC Gain | |
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| Improving INL by Calibration | |
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| Topologies Without an Op-Amp | |
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| The Voltage-Mode DAC | |
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| Two Important Notes Concerning Glitches | |
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| The Current-Mode (Current Steering) DAC | |
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| Op-Amps in Data Converters | |
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| Gain Bandwidth Product of the Noninverting Op-Amp Topology | |
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| Gain Bandwidth Product of the Inverting Op-Amp Topology | |
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| Op-Amp Gain | |
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| Op-Amp Unity Gain Frequency | |
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| Op-Amp Offset | |
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| Adding an Auxiliary Input Port | |
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| Implementing ADCs | |
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| Implementing the S/H | |
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| A Single-Ended to Differential Output S/H | |
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| The Cyclic ADC | |
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| Comparator Placement | |
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| Implementing Subtraction in the S/H | |
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| Understanding Output Swing | |
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| The Pipeline ADC | |
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| Using 1.5 Bits/Stage | |
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| Capacitor Error Averaging | |
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| Comparator Placement | |
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| Clock Generation | |
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| Offsets and Alternative Design Topologies | |
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| Dynamic CMFB | |
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| Layout of Pipelined ADCs | |
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| Integrator-Based CMOS Filters | |
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| Integrator Building Blocks | |
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| Lowpass Filters | |
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| Active-RC Integrators | |
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| Effects of Finite Op-Amp Gain Bandwidth Product | |
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| Active-RC SNR | |
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| MOSFET-C Integrators | |
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| Why use an Active Circuit (an Op-Amp) | |
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| g[subscript m]-C (Transconductor-C) Integrators | |
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| Common-Mode Feedback Considerations | |
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| A High-Frequency Transconductor | |
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| Discrete-Time Integrators | |
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| An Important Note | |
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| Exact Frequency Response of a First-Order Discrete- Time Digital (or Ideal SC) Filter | |
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| Filtering Topologies | |
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| The Bilinear Transfer Function | |
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| Active-RC Implementation | |
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| Transconductor-C Implementation | |
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| Switched-Capacitor Implementation | |
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| Digital Filter Implementation | |
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| The Canonic Form (or Standard Form) of a Digital Filter | |
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| The Biquadratic Transfer Function | |
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| Active-RC Implementation | |
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| Switched-Capacitor Implementation | |
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| High Q | |
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| Q Peaking and Instability | |
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| Transconductor-C Implementation | |
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| The Digital Biquad | |
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| Filters using Noise-Shaping | |
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| Removing Modulation Noise | |
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| Implementing the Multipliers | |
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| At the Bench | |
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| A Push-Pull Amplifier | |
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| Deadbug Prototyping | |
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| Probing | |
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| Testing the Circuit | |
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| A First-Order Noise-Shaping Modulator | |
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| Prototyping the Modulator | |
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| Measuring 1/f Noise | |
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| MOSFET Noise | |
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| Input-Referred Noise Voltage | |
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| Chopper Stabilization | |
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| A Discrete Analog Integrator | |
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| Clock Generation | |
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| Prototyping the Filter | |
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| Quantization Noise | |
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| Prototyping the ADC Circuit | |
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| Index | |
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| About the Author | |