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Preface | |
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Introduction | |
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ATM Switch Systems | |
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Basics of ATM networks | |
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ATM switch structure | |
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IP Router Systems | |
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Functions of IP routers | |
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Architectures of IP routers | |
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Design Criteria and Performance Requirements | |
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References | |
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Basics of Packet Switching | |
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Switching Concepts | |
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Internal link blocking | |
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Output port contention | |
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Head-of-line blocking | |
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Multicasting | |
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Call splitting | |
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Switch Architecture Classification | |
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Time division switching | |
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Space division switching | |
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Buffering strategies | |
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Performance of Basic Switches | |
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Input-buffered switches | |
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Output-buffered switches | |
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Completely shared-buffer switches | |
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References | |
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Input-Buffered Switches | |
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A Simple Switch Model | |
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Head-of-line blocking phenomenon | |
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Traffic models and related throughput results | |
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Methods for Improving Performance | |
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Increasing internal capacity | |
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Increasing scheduling efficiency | |
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Scheduling Algorithms | |
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Parallel iterative matching (PIM) | |
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Iterative round-robin matching (iRRM) | |
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Iterative round-robin with SLIP (iSLIP) | |
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Dual round-robin matching (DRRM) | |
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Round-robin greedy scheduling | |
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Design of round-robin arbiters/selectors | |
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Output-Queuing Emulation | |
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Most-Urgent-Cell-First-Algorithm (MUCFA) | |
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Chuang et al.'s results | |
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Lowest-Output-Occupancy-Cell-First Algorithm (LOOFA) | |
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References | |
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Shared-Memory Switches | |
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Linked-List Approach | |
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Content-Addressable Memory Approach | |
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Space--Time--Space Approach | |
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Multistage Shared-Memory Switches | |
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Washington University gigabit switch | |
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Concentrator-based growable switch architecture | |
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Multicast Shared-Memory Switches | |
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Shared-memory switch with a multicast logical queue | |
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Shared-memory switch with cell copy | |
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Shared-memory switch with address copy | |
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References | |
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Banyan-Based Switches | |
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Banyan Networks | |
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Batcher-Sorting Network | |
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Output Contention Resolution Algorithms | |
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Three-phase implementation | |
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Ring reservation | |
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The Sunshine Switch | |
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Deflection Routing | |
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Tandem banyan switch | |
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Shuffle-exchange network with deflection routing | |
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Dual shuffle-exchange network with error-correcting routing | |
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Multicast Copy Networks | |
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Broadcast banyan network | |
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Encoding process | |
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Concentration | |
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Decoding process | |
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Overflow and call splitting | |
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Overflow and input fairness | |
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References | |
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Knockout-Based Switches | |
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Single-Stage Knockout Switch | |
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Basic architecture | |
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Knockout concentration principle | |
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Construction of the concentrator | |
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Channel Grouping Principle | |
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Maximum throughput | |
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Generalized knockout principle | |
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A Two-Stage Multicast Output-Buffered ATM Switch | |
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Two-stage configuration | |
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Multicast grouping network | |
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Translation tables | |
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Multicast knockout principle | |
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A Fault-Tolerant Multicast Output-Buffered ATM Switch | |
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Fault model of switch element | |
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Fault detection | |
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Fault location and reconfiguration | |
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Performance analysis of reconfigured switch module | |
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Appendix | |
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References | |
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The Abacus Switch | |
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Basic Architecture | |
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Multicast Contention Resolution Algorithm | |
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Implementation of Input Port Controller | |
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Performance | |
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Maximum throughput | |
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Average delay | |
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Cell loss probability | |
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ATM Routing and Concentration Chip | |
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Enhanced Abacus Switch | |
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Memoryless multistage concentration network | |
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Buffered multistage concentration network | |
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Resequencing cells | |
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Complexity comparison | |
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Abacus Switch for Packet Switching | |
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Packet interleaving | |
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Cell interleaving | |
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References | |
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Crosspoint-Buffered Switches | |
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Overview of Crosspoint-Buffered Switches | |
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Scalable Distributed Arbitration Switch | |
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SDA structure | |
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Performance of SDA switch | |
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Multiple-QoS SDA Switch | |
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MSDA structure | |
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Performance of MSDA switch | |
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References | |
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The Tandem-Crosspoint Switch | |
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Overview of Input--Output-Buffered Switches | |
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TDXP Structure | |
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Basic architecture | |
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Unicasting operation | |
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Multicasting operation | |
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Performance of TDXP Switch | |
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References | |
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Clos-Network Switches | |
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Routing Properties and Scheduling Methods | |
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A Suboptimal Straight Matching Method for Dynamic Routing | |
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The ATLANTA Switch | |
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Basic architecture | |
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Distributed and random arbitration | |
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Multicasting | |
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The Continuous Round-Robin Dispatching Switch | |
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Basic architecture | |
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Concurrent round-robin dispatching (CRRD) scheme | |
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Desynchronization effect of CRRD | |
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The Path Switch | |
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Homogeneous capacity and route assignment | |
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Heterogeneous capacity assignment | |
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References | |
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Optical Packet Switches | |
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All-Optical Packet Switches | |
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The staggering switch | |
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ATMOS | |
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Duan's switch | |
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Optoelectronic Packet Switches | |
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HYPASS | |
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STAR-TRACK | |
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Cisneros and Brackett's Architecture | |
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BNR switch | |
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Wave-mux switch | |
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The 3M Switch | |
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Basic architecture | |
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Cell delineation unit | |
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VCI-overwrite unit | |
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Cell synchronization unit | |
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Optical Interconnection Network for Terabit IP Routers | |
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Introduction | |
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A terabit IP router architecture | |
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Router module and route controller | |
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Optical interconnection network | |
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Ping-pong arbitration unit | |
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OIN complexity | |
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Power budget analysis | |
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Crosstalk analysis | |
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References | |
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Wireless ATM Switches | |
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Wireless ATM Structure Overviews | |
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System considerations | |
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Wireless ATM protocol | |
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Wireless ATM Systems | |
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NEC's WATMnet prototype system | |
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Olivetti's radio ATM LAN | |
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Virtual connection tree | |
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BAHAMA wireless ATM LAN | |
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NTT's wireless ATM Access | |
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Other European projects | |
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Radio Access Layers | |
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Radio physical layer | |
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Medium access control layer | |
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Data link control layer | |
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Handoff in Wireless ATM | |
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Connection rerouting | |
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Buffering | |
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Cell routing in a COS | |
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Mobility-Support ATM Switch | |
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Design of a mobility-support switch | |
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Performance | |
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References | |
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IP Route Lookups | |
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IP Router Design | |
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Architectures of generic routers | |
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IP route lookup design | |
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IP Route Lookup Based on Caching Technique | |
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IP Route Lookup Based on Standard Trie Structure | |
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Patricia Tree | |
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Small Forwarding Tables for Fast Route Lookups | |
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Level 1 of data structure | |
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Levels 2 and 3 of data structure | |
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Performance | |
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Route Lookups in Hardware at Memory Access Speeds | |
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The DIR-24-8-BASIC scheme | |
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Performance | |
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IP Lookups Using Multiway Search | |
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Adapting binary search for best matching prefix | |
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Precomputed 16-bit prefix table | |
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Multiway binary search: exploiting the cache line | |
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Performance | |
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IP Route Lookups for Gigabit Switch Routers | |
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Lookup algorithms and data structure construction | |
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Performance | |
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IP Route Lookups Using Two-Trie Structure | |
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IP route lookup algorithm | |
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Prefix update algorithms | |
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Performance | |
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References | |
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Sonet and ATM Protocols | |
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ATM Protocol Reference Model | |
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Synchronous Optical Network (SONET) | |
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SONET sublayers | |
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STS-N signals | |
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SONET overhead bytes | |
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Scrambling and descrambling | |
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Frequency justification | |
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Automatic protection switching (APS) | |
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STS-3 versus STS-3c | |
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OC-N multiplexer | |
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Sub-Layer Functions in Reference Model | |
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Asynchronous Transfer Mode (ATM) | |
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Virtual path/virtual channel identifier (VPI/VCI) | |
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Payload type identifier (PTI) | |
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Cell loss priority (CLP) | |
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Pre-defined header field values | |
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ATM Adaptation Layer (AAL) | |
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AAL type 1 (AAL1) | |
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AAL type 2 (AAL2) | |
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AAL types 3/4 (AAL3/4) | |
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AAL type 5 (AAL5) | |
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References | |
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Index | |