Skip to content

Broadband Packet Switching Technologies A Practical Guide to ATM Switches and IP Routers

Spend $50 to get a free DVD!

ISBN-10: 0471004545

ISBN-13: 9780471004547

Edition: 2001

Authors: H. Jonathan Chao, Cheuk H. Lam, Eiji Oki

List price: $174.75
Shipping box This item qualifies for FREE shipping.
Blue ribbon 30 day, 100% satisfaction guarantee!
what's this?
Rush Rewards U
Members Receive:
Carrot Coin icon
XP icon
You have reached 400 XP and carrot coins. That is the daily max!

Description:

At a time when increasing amounts of data are being distributed on communication networks, the design of high-speed, reliable switching systems is of central importance. This book provides systematic coverage of the main packet-switching architectures.
Customers also bought

Book details

List price: $174.75
Copyright year: 2001
Publisher: John Wiley & Sons, Incorporated
Publication date: 10/11/2001
Binding: Hardcover
Pages: 480
Size: 6.50" wide x 9.75" long x 1.25" tall
Weight: 1.738
Language: English

Preface
Introduction
ATM Switch Systems
Basics of ATM networks
ATM switch structure
IP Router Systems
Functions of IP routers
Architectures of IP routers
Design Criteria and Performance Requirements
References
Basics of Packet Switching
Switching Concepts
Internal link blocking
Output port contention
Head-of-line blocking
Multicasting
Call splitting
Switch Architecture Classification
Time division switching
Space division switching
Buffering strategies
Performance of Basic Switches
Input-buffered switches
Output-buffered switches
Completely shared-buffer switches
References
Input-Buffered Switches
A Simple Switch Model
Head-of-line blocking phenomenon
Traffic models and related throughput results
Methods for Improving Performance
Increasing internal capacity
Increasing scheduling efficiency
Scheduling Algorithms
Parallel iterative matching (PIM)
Iterative round-robin matching (iRRM)
Iterative round-robin with SLIP (iSLIP)
Dual round-robin matching (DRRM)
Round-robin greedy scheduling
Design of round-robin arbiters/selectors
Output-Queuing Emulation
Most-Urgent-Cell-First-Algorithm (MUCFA)
Chuang et al.'s results
Lowest-Output-Occupancy-Cell-First Algorithm (LOOFA)
References
Shared-Memory Switches
Linked-List Approach
Content-Addressable Memory Approach
Space--Time--Space Approach
Multistage Shared-Memory Switches
Washington University gigabit switch
Concentrator-based growable switch architecture
Multicast Shared-Memory Switches
Shared-memory switch with a multicast logical queue
Shared-memory switch with cell copy
Shared-memory switch with address copy
References
Banyan-Based Switches
Banyan Networks
Batcher-Sorting Network
Output Contention Resolution Algorithms
Three-phase implementation
Ring reservation
The Sunshine Switch
Deflection Routing
Tandem banyan switch
Shuffle-exchange network with deflection routing
Dual shuffle-exchange network with error-correcting routing
Multicast Copy Networks
Broadcast banyan network
Encoding process
Concentration
Decoding process
Overflow and call splitting
Overflow and input fairness
References
Knockout-Based Switches
Single-Stage Knockout Switch
Basic architecture
Knockout concentration principle
Construction of the concentrator
Channel Grouping Principle
Maximum throughput
Generalized knockout principle
A Two-Stage Multicast Output-Buffered ATM Switch
Two-stage configuration
Multicast grouping network
Translation tables
Multicast knockout principle
A Fault-Tolerant Multicast Output-Buffered ATM Switch
Fault model of switch element
Fault detection
Fault location and reconfiguration
Performance analysis of reconfigured switch module
Appendix
References
The Abacus Switch
Basic Architecture
Multicast Contention Resolution Algorithm
Implementation of Input Port Controller
Performance
Maximum throughput
Average delay
Cell loss probability
ATM Routing and Concentration Chip
Enhanced Abacus Switch
Memoryless multistage concentration network
Buffered multistage concentration network
Resequencing cells
Complexity comparison
Abacus Switch for Packet Switching
Packet interleaving
Cell interleaving
References
Crosspoint-Buffered Switches
Overview of Crosspoint-Buffered Switches
Scalable Distributed Arbitration Switch
SDA structure
Performance of SDA switch
Multiple-QoS SDA Switch
MSDA structure
Performance of MSDA switch
References
The Tandem-Crosspoint Switch
Overview of Input--Output-Buffered Switches
TDXP Structure
Basic architecture
Unicasting operation
Multicasting operation
Performance of TDXP Switch
References
Clos-Network Switches
Routing Properties and Scheduling Methods
A Suboptimal Straight Matching Method for Dynamic Routing
The ATLANTA Switch
Basic architecture
Distributed and random arbitration
Multicasting
The Continuous Round-Robin Dispatching Switch
Basic architecture
Concurrent round-robin dispatching (CRRD) scheme
Desynchronization effect of CRRD
The Path Switch
Homogeneous capacity and route assignment
Heterogeneous capacity assignment
References
Optical Packet Switches
All-Optical Packet Switches
The staggering switch
ATMOS
Duan's switch
Optoelectronic Packet Switches
HYPASS
STAR-TRACK
Cisneros and Brackett's Architecture
BNR switch
Wave-mux switch
The 3M Switch
Basic architecture
Cell delineation unit
VCI-overwrite unit
Cell synchronization unit
Optical Interconnection Network for Terabit IP Routers
Introduction
A terabit IP router architecture
Router module and route controller
Optical interconnection network
Ping-pong arbitration unit
OIN complexity
Power budget analysis
Crosstalk analysis
References
Wireless ATM Switches
Wireless ATM Structure Overviews
System considerations
Wireless ATM protocol
Wireless ATM Systems
NEC's WATMnet prototype system
Olivetti's radio ATM LAN
Virtual connection tree
BAHAMA wireless ATM LAN
NTT's wireless ATM Access
Other European projects
Radio Access Layers
Radio physical layer
Medium access control layer
Data link control layer
Handoff in Wireless ATM
Connection rerouting
Buffering
Cell routing in a COS
Mobility-Support ATM Switch
Design of a mobility-support switch
Performance
References
IP Route Lookups
IP Router Design
Architectures of generic routers
IP route lookup design
IP Route Lookup Based on Caching Technique
IP Route Lookup Based on Standard Trie Structure
Patricia Tree
Small Forwarding Tables for Fast Route Lookups
Level 1 of data structure
Levels 2 and 3 of data structure
Performance
Route Lookups in Hardware at Memory Access Speeds
The DIR-24-8-BASIC scheme
Performance
IP Lookups Using Multiway Search
Adapting binary search for best matching prefix
Precomputed 16-bit prefix table
Multiway binary search: exploiting the cache line
Performance
IP Route Lookups for Gigabit Switch Routers
Lookup algorithms and data structure construction
Performance
IP Route Lookups Using Two-Trie Structure
IP route lookup algorithm
Prefix update algorithms
Performance
References
Sonet and ATM Protocols
ATM Protocol Reference Model
Synchronous Optical Network (SONET)
SONET sublayers
STS-N signals
SONET overhead bytes
Scrambling and descrambling
Frequency justification
Automatic protection switching (APS)
STS-3 versus STS-3c
OC-N multiplexer
Sub-Layer Functions in Reference Model
Asynchronous Transfer Mode (ATM)
Virtual path/virtual channel identifier (VPI/VCI)
Payload type identifier (PTI)
Cell loss priority (CLP)
Pre-defined header field values
ATM Adaptation Layer (AAL)
AAL type 1 (AAL1)
AAL type 2 (AAL2)
AAL types 3/4 (AAL3/4)
AAL type 5 (AAL5)
References
Index