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Preface | |
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Signals, Filters, and Tools | |
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Sinusoidal Signals | |
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The Pendulum Analogy | |
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Describing Amplitude in the x-y Plane | |
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In-Phase and Quadrature Signals | |
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The Complex (z-) Plane | |
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Comb Filters | |
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The Digital Comb Filter | |
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The Digital Differentiator | |
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An Intuitive Discussion of the z-Plane | |
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Comb Filters with Multiple Delay Elements | |
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The Digital Integrator | |
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The Delaying Integrator | |
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An Important Note | |
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Representing Signals | |
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Exponential Fourier Series | |
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Fourier Transform | |
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Dirac Delta Function (Unit Impulse Response) | |
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Sampling and Aliasing | |
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Sampling | |
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Impulse Sampling | |
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A Note Concerning the AAF and the RCF | |
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Time Domain Description of Reconstruction | |
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An Important Note | |
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Decimation | |
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The Sample-and-Hold (S/H) | |
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S/H Spectral Response | |
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The Reconstruction Filter (RCF) | |
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Circuit Concerns for Implementing the S/H | |
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An Example | |
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The Track-and-Hold (T/H) | |
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Interpolation | |
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Zero Padding | |
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Hold Register | |
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Linear Interpolation | |
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K-Path Sampling | |
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Switched-Capacitor Circuits | |
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Non-Overlapping Clock Generation | |
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Circuits | |
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Implementing the S/H | |
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Finite Op-Amp Gain-Bandwidth Product | |
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Autozeroing | |
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Correlated Double Sampling (CDS) | |
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Selecting Capacitor Sizes | |
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The S/H with Gain | |
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Implementing Subtraction in the S/H | |
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A Single-Ended to Differential Output S/H | |
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The Discrete Analog Integrator (DAI) | |
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A Note Concerning Block Diagrams | |
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Fully-Differential DAI | |
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DAI Noise Performance | |
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Analog Filters | |
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Integrator Building Blocks | |
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Lowpass Filters | |
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Active-RC Integrators | |
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Effects of Finite Op-Amp Gain Bandwidth Product, f[subscript un] | |
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Active-RC SNR | |
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MOSFET-C Integrators | |
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Why Use an Active Circuit (an Op-Amp)? | |
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g[subscript m]-C (Transconductor-C) Integrators | |
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Common-Mode Feedback Considerations | |
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A High-Frequency Transconductor | |
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Discrete-Time Integrators | |
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An Important Note | |
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Exact Frequency Response of an Ideal Discrete-Time Filter | |
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Filtering Topologies | |
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The Bilinear Transfer Function | |
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Active-RC Implementation | |
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Transconductor-C Implementation | |
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Switched-Capacitor Implementation | |
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The Biquadratic Transfer Function | |
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Active-RC Implementation | |
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Switched-Capacitor Implementation | |
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High Q | |
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Q Peaking and Instability | |
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Transconductor-C Implementation | |
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Digital Filters | |
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SPICE Models for DACs and ADCs | |
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The Ideal DAC | |
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SPICE Modeling the Ideal DAC | |
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The Ideal ADC | |
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Number Representation | |
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Increasing Word Size (Extending the Sign-Bit) | |
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Adding Numbers and Overflow | |
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Subtracting Numbers in Two's Complement Format | |
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Sinc-Shaped Digital Filters | |
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The Counter | |
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Aliasing | |
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The Accumulate-and-Dump | |
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Lowpass Sinc Filters | |
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Averaging without Decimation: A Review | |
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Cascading Sinc Filters | |
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Finite and Infinite Impulse Response Filters | |
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Bandpass and Highpass Sinc Filters | |
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Canceling Zeroes to Create Highpass and Bandpass Filters | |
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Frequency Sampling Filters | |
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Interpolation using Sinc Filters | |
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Additional Control | |
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Cascade of Integrators and Combs | |
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Decimation using Sinc Filters | |
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Filtering Topologies | |
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FIR Filters | |
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Stability and Overflow | |
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Overflow | |
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The Bilinear Transfer Function | |
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The Canonic Form (or Standard Form) of a Digital Filter | |
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General Canonic Form of a Recursive Filter | |
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The Biquadratic Transfer Function | |
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Comparing Biquads to Sinc-Shaped Filters | |
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A Comment Concerning Multiplications | |
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Data Converter SNR | |
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Quantization Noise | |
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Viewing the Quantization Noise Spectrum Using Simulations | |
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Bennett's Criteria | |
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An Important Note | |
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RMS Quantization Noise Voltage | |
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Treating Quantization Noise as a Random Variable | |
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Quantization Noise Voltage Spectral Density | |
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Calculating Quantization Noise from a SPICE Spectrum | |
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Power Spectral Density | |
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Signal-to-Noise Ratio (SNR) | |
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Effective Number of Bits | |
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Coherent Sampling | |
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Signal-to-Noise Plus Distortion Ratio | |
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Spurious Free Dynamic Range | |
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Dynamic Range | |
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Specifying SNR and SNDR | |
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Clock Jitter | |
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Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements | |
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A Practical Note | |
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A Tool: The Spectral Density | |
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The Spectral Density of Deterministic Signals: An Overview | |
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The Spectral Density of Random Signals: An Overview | |
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Specifying Phase Noise from Measured Data | |
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Improving SNR using Averaging | |
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An Important Note | |
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Using Averaging to Improve SNR | |
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Ideal Signal-to-Noise Ratio | |
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Linearity Requirements | |
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Adding a Noise Dither | |
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Jitter | |
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Anti-Aliasing Filter | |
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Using Feedback to Improve SNR | |
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Data Converter Design Basics | |
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The One-Bit ADC and DAC | |
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Passive Noise-Shaping | |
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Signal-to-Noise Ratio | |
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Decimating and Filtering the Modulator's Output | |
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SNR Calculation using a Sinc Filter | |
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Offset, Matching, and Linearity | |
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Resistor Mismatch | |
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The Feedback DAC | |
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DAC Offset | |
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Linearity of the First-Order Modulator | |
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Dead Zones | |
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Improving SNR and Linearity | |
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Second-Order Passive Noise-Shaping | |
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Passive Noise-Shaping Using Switched-Capacitors | |
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Increasing SNR using K-Paths | |
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Revisiting Switched-Capacitor Implementations | |
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Effects of the Added Amplifier on Linearity | |
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Improving Linearity Using an Active Circuit | |
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Second-Order Noise-Shaping | |
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Signal-to-Noise Ratio | |
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Discussion | |
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Noise-Shaping Data Converters | |
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First-Order Noise Shaping | |
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A Digital First-Order NS Demodulator | |
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Modulation Noise in First-Order NS Modulators | |
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RMS Quantization Noise in a First-Order Modulator | |
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Decimating and Filtering the Output of a NS Modulator | |
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Pattern Noise from DC Inputs (Limit Cycle Oscillations) | |
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Integrator and Forward Modulator Gain | |
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Comparator Gain, Offset, Noise, and Hysteresis | |
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Op-Amp Gain (Integrator Leakage) | |
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Op-Amp Settling Time | |
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Op-Amp Offset | |
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Op-Amp Input-Referred Noise | |
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Practical Implementation of the First-Order NS Modulator | |
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Second-Order Noise-Shaping | |
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Second-Order Modulator Topology | |
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Integrator Gain | |
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Implementing Feedback Gains in the DAI | |
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Using Two Delaying Integrators to Implement the Second-Order Modulator | |
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Selecting Modulator (Integrator) Gains | |
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Noise-Shaping Topologies | |
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Higher-Order Modulators | |
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M[superscript th]-Order Modulator Topology | |
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Filtering the Output of an M[superscript th]-Order NS Modulator | |
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Implementing Higher-Order, Single-Stage Modulators | |
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Multi-Bit Modulators | |
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Simulating a Multibit NS Modulator Using SPICE | |
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Error Feedback | |
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Implementation Concerns | |
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Cascaded Modulators | |
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Second-Order (1-1) Modulators | |
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Third-Order (1-1-1) Modulators | |
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Third-Order (2-1) Modulators | |
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Implementing the Additional Summing Input | |
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Bandpass Data Converters | |
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Continuous-Time Bandpass Noise-Shaping | |
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Passive-Component Bandpass Modulators | |
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An Important Note | |
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Active-Component Bandpass Modulators | |
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Signal-to-Noise Ratio | |
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Modulators for Conversion at Radio Frequencies | |
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Switched-Capacitor Bandpass Noise-Shaping | |
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Switched-Capacitor Resonators | |
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Second-Order Modulators | |
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Fourth-Order Modulators | |
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A Common Error | |
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A Comment about 1/f Noise | |
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Digital I/Q Extraction to Baseband | |
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A High-Speed Data Converter | |
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The Topology | |
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Clock Signals | |
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Path Settling Time | |
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Implementation | |
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Filtering | |
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Examples | |
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Direction | |
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Discussion | |
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Understanding the Clock Signals | |
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Practical Implementation | |
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Generating the Clock Signals | |
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The Components | |
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The Switched-Capacitors | |
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The Amplifier | |
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The Clocked Comparator | |
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The ADC | |
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Conclusion | |
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Index | |