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| About This Book | |
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| The MindShare Architecture Series | |
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| Cautionary Note | |
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| Intended Audience | |
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| Prerequisite Knowledge | |
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| Topics and Organization | |
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| Documentation Conventions | |
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| PCI Express | |
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| Hexadecimal Notation | |
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| Binary Notation | |
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| Decimal Notation | |
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| Bits Versus Bytes Notation | |
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| Bit Fields | |
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| Active Signal States | |
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| Visit Our Web Site | |
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| We Want Your Feedback | |
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| The Big Picture | |
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| Architectural Perspective | |
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| Introduction To PCI Express | |
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| Predecessor Buses Compared | |
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| I/O Bus Architecture Perspective | |
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| The PCI Express Way | |
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| PCI Express Specifications | |
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| Architecture Overview | |
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| Introduction to PCI Express Transactions | |
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| PCI Express Device Layers | |
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| Example of a Non-Posted Memory Read Transaction | |
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| Hot Plug | |
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| PCI Express Performance and Data Transfer Efficiency | |
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| Transaction Protocol | |
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| Address Spaces & Transaction Routing | |
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| Introduction | |
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| Two Types of Local Link Traffic | |
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| Transaction Layer Packet Routing Basics | |
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| Applying Routing Mechanisms | |
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| Plug-And-Play Configuration of Routing Options | |
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| Packet-Based Transactions | |
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| Introduction to the Packet-Based Protocol | |
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| Transaction Layer Packets | |
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| Data Link Layer Packets | |
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| ACK/NAK Protocol | |
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| Reliable Transport of TLPs Across Each Link | |
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| Elements of the ACK/NAK Protocol | |
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| ACK/NAK DLLP Format | |
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| ACK/NAK Protocol Details | |
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| Error Situations Reliably Handled by ACK/NAK Protocol | |
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| ACK/NAK Protocol Summary | |
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| Recommended Priority To Schedule Packets | |
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| Some More Examples | |
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| Switch Cut-Through Mode | |
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| QoS/TCs/VCs and Arbitration | |
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| Quality of Service | |
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| Perspective on QOS/TC/VC and Arbitration | |
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| Traffic Classes and Virtual Channels | |
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| Arbitration | |
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| Flow Control | |
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| Flow Control Concept | |
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| Flow Control Buffers | |
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| Introduction to the Flow Control Mechanism | |
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| Flow Control Packets | |
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| Operation of the Flow Control Model - An Example | |
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| Infinite Flow Control Advertisement | |
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| The Minimum Flow Control Advertisement | |
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| Flow Control Initialization | |
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| Flow Control Updates Following FC_INIT | |
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| Transaction Ordering | |
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| Introduction | |
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| Producer/Consumer Model | |
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| Native PCI Express Ordering Rules | |
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| Relaxed Ordering | |
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| Modified Ordering Rules Improve Performance | |
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| Support for PCI Buses and Deadlock Avoidance | |
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| Interrupts | |
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| Two Methods of Interrupt Delivery | |
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| Message Signaled Interrupts | |
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| Legacy PCI Interrupt Delivery | |
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| Devices May Support Both MSI and Legacy Interrupts | |
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| Special Consideration for Base System Peripherals | |
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| Error Detection and Handling | |
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| Background | |
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| Introduction to PCI Express Error Management | |
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| Sources of PCI Express Errors | |
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| Error Classifications | |
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| How Errors are Reported | |
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| Baseline Error Detection and Handling | |
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| Advanced Error Reporting Mechanisms | |
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| Summary of Error Logging and Reporting | |
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| The Physical Layer | |
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| Physical Layer Logic | |
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| Physical Layer Overview | |
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| Transmit Logic Details | |
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| Receive Logic Details | |
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| Physical Layer Error Handling | |
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| Electrical Physical Layer | |
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| Electrical Physical Layer Overview | |
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| High Speed Electrical Signaling | |
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| LVDS Eye Diagram | |
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| Transmitter Driver Characteristics | |
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| Input Receiver Characteristics | |
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| Electrical Physical Layer State in Power States | |
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| System Reset | |
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| Two Categories of System Reset | |
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| Reset Exit | |
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| Link Wakeup from L2 Low Power State | |
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| Link Initialization & Training | |
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| Link Initialization and Training Overview | |
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| Ordered-Sets Used During Link Training and Initialization | |
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| Link Training and Status State Machine (LTSSM) | |
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| Detailed Description of LTSSM States | |
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| LTSSM Related Configuration Registers | |
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| Power-Related Topics | |
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| Power Budgeting | |
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| Introduction to Power Budgeting | |
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| The Power Budgeting Elements | |
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| Slot Power Limit Control | |
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| The Power Budget Capabilities Register Set | |
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| Power Management | |
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| Introduction | |
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| Primer on Configuration Software | |
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| Function Power Management | |
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| Introduction to Link Power Management | |
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| Link Active State Power Management | |
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| Software Initiated Link Power Management | |
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| Link Wake Protocol and PME Generation | |
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| Optional Topics | |
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| Hot Plug | |
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| Background | |
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| Hot Plug in the PCI Express Environment | |
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| Elements Required to Support Hot Plug | |
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| Card Removal and Insertion Procedures | |
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| Standardized Usage Model | |
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| Standard Hot Plug Controller Signaling Interface | |
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| The Hot-Plug Controller Programming Interface | |
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| Slot Numbering | |
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| Quiescing Card and Driver | |
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| The Primitives | |
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| Add-in Cards and Connectors | |
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| Introduction | |
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| Form Factors Under Development | |
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| PCI Express Configuration | |
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| Configuration Overview | |
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| Definition of Device and Function | |
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| Definition of Primary and Secondary Bus | |
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| Topology Is Unknown At Startup | |
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| Each Function Implements a Set of Configuration Registers | |
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| Host/PCI Bridge's Configuration Registers | |
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| Configuration Transactions Are Originated by the Processor | |
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| Configuration Transactions Are Routed Via Bus, Device, and Function Number | |
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| How a Function Is Discovered | |
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| How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function | |
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| Configuration Mechanisms | |
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| Introduction | |
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| PCI-Compatible Configuration Mechanism | |
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| PCI Express Enhanced Configuration Mechanism | |
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| Type 0 Configuration Request | |
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| Type 1 Configuration Request | |
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| Example PCI-Compatible Configuration Access | |
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| Example Enhanced Configuration Access | |
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| Initial Configuration Accesses | |
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| PCI Express Enumeration | |
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| Introduction | |
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| Enumerating a System With a Single Root Complex | |
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| Enumerating a System With Multiple Root Complexes | |
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| A Multifunction Device Within a Root Complex or a Switch | |
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| An Endpoint Embedded in a Switch or Root Complex | |
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| Memorize Your Identity | |
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| Root Complex Register Blocks (RCRBs) | |
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| Miscellaneous Rules | |
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| PCI Compatible Configuration Registers | |
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| Header Type 0 | |
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| Header Type 1 | |
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| PCI-Compatible Capabilities | |
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| Expansion ROMs | |
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| ROM Purpose--Device Can Be Used In Boot Process | |
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| ROM Detection | |
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| ROM Shadowing Required | |
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| ROM Content | |
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| Execution of Initialization Code | |
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| Introduction to Open Firmware | |
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| Express-Specific Configuration Registers | |
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| Introduction | |
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| PCI Express Capability Register Set | |
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| PCI Express Extended Capabilities | |
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| RCRB | |
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| Appendices | |
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| Test, Debug and Verification | |
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| Markets & Applications for the PCI Express Architecture | |
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| Implementing Intelligent Adapters and Multi-Host Systems With PCI Express Technology | |
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| Class Codes | |
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| Locked Transactions Series | |
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| Index | |