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| Staff | |
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| About This Book | |
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| The MindShare Architecture Series | |
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| Cautionary Note | |
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| What This Book Covers | |
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| What This Book Does Not Cover | |
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| Organization of This Book | |
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| Who This Book Is For | |
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| Prerequisite Knowledge | |
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| Documentation Conventions | |
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| Hexadecimal Notation | |
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| Binary Notation | |
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| Decimal Notation | |
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| Signal Name Representation | |
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| Warning | |
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| Identification of Bit Fields (Logical Groups of Bits or Signals) | |
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| Register Field References | |
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| Resources | |
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| Visit Our Web Site | |
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| We Want Your Feedback | |
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| System Overview | |
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| System Overview | |
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| Introduction | |
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| What Is a Cluster? | |
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| What Is a Quad or 4-Way System? | |
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| Bootstrap Processor | |
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| Starting Up Other Processors | |
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| Relationship of Processors to Main Memory | |
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| Processors' Relationships to Each Other | |
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| Host/PCI Bridges | |
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| Bridges' Relationship to Processors | |
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| Bridges' Relationship to PCI Masters and Main Memory | |
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| Bridges' Relationship to PCI Targets | |
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| Bridges' Relationship to EISA or ISA Targets | |
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| Bridges' Relationship to Each Other | |
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| Bridge's Relationship to EISA and ISA Masters and DMA | |
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| Processor's Hardware Characteristics | |
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| Hardware Section 1: The Processor | |
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| Processor Overview | |
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| Two Bus Interfaces | |
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| External Bus | |
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| Bus on Earlier Processors Inefficient for Multiprocessing | |
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| Pentium Bus Has Limited Transaction Pipelining Capability | |
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| Pentium Pro Bus Tuned for Multiprocessing | |
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| IA = Legacy | |
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| Instruction Set | |
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| IA Instructions Vary in Length and Are Complex | |
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| Pentium Pro Translates IA Instructions into RISC Instructions | |
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| In-Order Front End | |
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| Out-of-Order Middle | |
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| In-Order Rear End | |
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| Register Set | |
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| IA Register Set Is Small | |
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| Pentium Pro Has 40 General-Purpose Registers | |
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| Elimination of False Register Dependencies | |
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| Introduction to the Internal Architecture | |
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| Processor Power-On Configuration | |
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| Automatically Configured Features | |
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| Example of Captured Configuration Information | |
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| Setup and Hold Time Requirements | |
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| Run BIST Option | |
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| Error Observation Options | |
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| In-Order Queue Depth Selection | |
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| Power-On Restart Address Selection | |
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| FRC Mode Enable/Disable | |
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| APIC ID Selection | |
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| Selecting Tri-State Mode | |
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| Processor Core Speed Selection | |
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| Processor's Agent and APIC ID Assignment | |
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| FRC Mode | |
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| Program-Accessible Startup Features | |
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| Processor Startup | |
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| Selection of Processor's Agent and APIC IDs | |
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| Processor's State After Reset | |
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| EDX Contains Processor Identification Info | |
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| State of Caches and Processor's Ability to Cache | |
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| Selection of Bootstrap Processor (BSP) | |
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| Introduction | |
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| BSP Selection Process | |
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| APIC Arbitration Background | |
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| Startup APIC Arbitration ID Assignment | |
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| BSP Selection Process | |
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| Example of APIC Bus Traffic Captured during BSP Selection | |
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| Initial BSP Memory Accesses | |
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| General | |
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| When Caching Disabled, Prefetcher Always Does 32-byte Code Reads | |
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| State 2: 1st Line Read (and jump at FFFFFFF0h executed) | |
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| State 10: Branch Trace Message for Jump at FFFFFFF0h | |
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| State 16: Branch Target Line Read (and 2nd jump executed) | |
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| State 26: Branch Trace Message for 2nd Jump | |
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| State 32: CLI Fetched and Executed | |
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| State 42: CLD Fetched and Executed | |
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| State 50: JMP Rel/Fwd Fetched and Executed | |
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| State 58: Branch Trace Message for JMP Rel/F | |