High Speed Signaling Jitter Modeling, Analysis, and Budgeting

Name: High Speed Signaling Jitter Modeling, Analysis, and Budgeting
Availability: OutOfStock
ISBN: 9780132826914

ISBN-10: 0132826917

ISBN-13: 9780132826914

Edition: 2012 (Revised)

Authors: Kyung Suk Oh, Xing Chao Yuan

List price: $130.00

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As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial, and high-speed signal integrity engineering has grown into one of today's most important engineering disciplines. This book brings together cutting-edge contributions from the field's most respected practitioners and researchers, including leaders at Rambus, MIT, and the University of California, Berkeley. Edited by pioneering experts Dan Oh and Chuck Yuan, these contributors illuminate the newest design challenges in signal integrity and power integrity (SI/PI). They summarize emerging issues and new modeling/analysis methodologies used by leading…

Book details

List price: $130.00
Copyright year: 2012
Publisher: Prentice Hall PTR
Publication date: 10/6/2011
Binding: Hardcover
Pages: 528
Size: 7.00" wide x 9.00" long x 1.25" tall
Weight: 2.134



Preface



Introduction



Signal Integrity Analysis Trends



Challenges of High-Speed Signal Integrity Design



Organization of This Book


References



High-Speed Signaling Basics



I/O Signaling Basics and Components



Noise Sources



Jitter Basics and Decompositions



Summary


References



Channel Modeling and Design



Channel Modeling and Design Methodology



Channel Design Methodology



Channel Modeling Methodology



Modeling with Electromagnetic Field Solvers



Backplane Channel Modeling Example



Summary


References



Network Parameters



Generalized Network Parameters for Multi-Conductor Systems



Preparing an Accurate S-Parameter Time-Domain Model



Passivity Conditions



Causality Conditions



Summary


References



Transmission Lines



Transmission Line Theory



Forward and Backward Crosstalk



Time-Domain Simulation of Transmission Lines



Modeling Transmission Line from Measurements



On-Chip Wire Modeling



Comparison of On-Chip, Package, and PCB Traces



Summary


References



Analyzing Link Performance



Channel Voltage and Timing Budget



Timing Budget Equation and Components



Fibre Channel Dual-Dirac Model



Component-Level Timing Budget



Pitfalls of Timing Budget Equation



Voltage Budget Equations and Components



Summary


References



Manufacturing Variation Modeling



Introduction to the Taguchi Method



DDR DRAM Command/Address Channel Example



Backplane Link Modeling Example



Summary



Appendix


References



Link BER Modeling and Simulation



Historical Background and Chapter Organization



Statistical Link BER Modeling Framework



Intersymbol Interference Modeling



Transmitter and Receiver Jitter Modeling



Periodic Jitter Modeling



Summary


References



Fast Time-Domain Channel Simulation Techniques



Fast Time-Domain Simulation Flow Overview



Fast System Simulation Techniques



Simultaneous Switching Noise Example



Comparison of Jitter Modeling Methods



Peak Distortion Analysis



Summary


References



Clock Models in Link BER Analysis



Independent and Common Clock Jitter Models



Modeling Common Clocking Schemes



CDR Circuitry Modeling



Passive Channel JIF and Jitter Amplification



Summary


References



Supply Noise and Jitter



Overview of Power Integrity Engineering



PDN Design Goals and Supply Budget



Power Supply Budget Components



Deriving a Power Supply Budget



Supply Noise Analysis Methodology



Steps in Power Supply Noise Analysis



Summary


References



SSN Modeling and Simulation



SSN Modeling Challenges



SI and PI Co-Simulation Methodology



Signal Current Loop and Supply Noise



Additional SSN Modeling Topics



Case Study: DDR2 SSN Analysis for Consumer Applications



Summary


References



SSN Reduction Codes and Signaling



Data Bus Inversion Code



Pseudo Differential Signaling Based on 4b6b Code



Summary


References



Supply Noise and Jitter Characterization



Importance of Supply Noise Induced Jitter



Overview of PSIJ Modeling Methodology



Noise and Jitter Simulation Methodology



Case Study



Summary


References



Substrate Noise Induced Jitter



Introduction



Modeling Techniques



Measurement Techniques



Case Study



Summary


References



Advanced Topics



On-Chip Link Measurement Techniques



Shmoo and BER Eye Diagram Measurements



Capturing Signal Waveforms



Link Performance Measurement and Correlation



On-Chip Supply Noise Measurement Techniques



Advanced Power Integrity Measurements



Summary


References



Signal Conditioning



Single-Bit Response



Equalization Techniques



Equalization Adaptation Algorithms



CDR and Equalization Adaptation Interaction



ADC-Based Receive Equalization



Future of High-Speed Wireline Equalization



Summary


References



Applications



XDR: High-Performance Differential Memory System



Mobile XDR: Low Power Differential Memory System



Main Memory Systems beyond DDR3



Future Signaling Systems


References


Index