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(NOTE: Most chapters conclude with References, Drill Problems, and Exercises.) | |
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Introduction | |
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About Digital Design | |
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Analog versus Digital | |
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Digital Devices | |
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Electronic Aspects of Digital Design | |
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Software Aspects of Digital Design | |
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Integrated Circuits | |
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Programmable Logic Devices | |
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Application-Specific ICs | |
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Printed-Circuit Boards | |
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Digital-Design Levels | |
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The Name of the Game | |
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Going Forward | |
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Number Systems and Codes | |
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Positional Number Systems | |
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Octal and Hexadecimal Numbers | |
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General Positional-Number-System Conversions | |
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Addition and Subtraction of Nondecimal Numbers | |
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Representation of Negative Numbers | |
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Two's-Complement Addition and Subtraction | |
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Ones'-Complement Addition and Subtraction | |
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Binary Multiplication | |
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Binary Division | |
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Binary Codes for Decimal Numbers | |
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Gray Code | |
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Character Codes | |
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Codes for Actions, Conditions, and States | |
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n-Cubes and Distance | |
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Codes for Detecting and Correcting Errors | |
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Codes for Serial Data Transmission and Storage | |
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Digital Circuits | |
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Logic Signals and Gates | |
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Logic Families | |
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CMOS Logic | |
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Electrical Behavior of CMOS Circuits | |
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CMOS Steady-State Electrical Behavior | |
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CMOS Dynamic Electrical Behavior | |
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Other CMOS Input and Output Structures | |
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CMOS Logic Families | |
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Bipolar Logic | |
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Transistor-Transistor Logic | |
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TTL Families | |
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CMOS/TTL Interfacing | |
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Low-Voltage CMOS Logic and Interfacing | |
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Emitter-Coupled Logic | |
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Combinational Logic Design Principles | |
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Switching Algebra | |
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Combinational-Circuit Analysis | |
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Combinational- Circuit Synthesis | |
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Programmed Minimization Methods | |
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Timing Hazards | |
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The ABEL Hardware Description Language | |
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The VHDL Hardware Description Language | |
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Hardware Description Languages | |
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HDL-Based Digital Design | |
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The ABEL Hardware Description Language | |
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The VHDL Hardware Description Language | |
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Combinational Logic Design Practices | |
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Documentation Standards | |
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Circuit Timing | |
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Combinational PLDs | |
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Decoders | |
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Encoders | |
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Three-State Devices | |
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Multiplexers | |
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Exclusive-OR Gates and Parity Circuits | |
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Comparators | |
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Adders, Subtractors, and ALUs | |
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Combinational Multipliers | |
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Sequential Logic Design Principles | |
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Bistable Elements | |
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Latches and Flip-Flops | |
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Clocked Synchronous State-Machine Analysis | |
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Clocked Synchronous State-Machine Design | |
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Designing State Machines Using State Diagrams | |
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State-Machine Synthesis Using Transition Lists | |
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Another State-Machine Design Example | |
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Decomposing State Machines | |
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Feedback Sequential Circuits | |
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Feedback Sequential-Circuit Design | |
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ABEL Sequential-Circuit Design Features | |
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VHDL Sequential-Circuit Design Features | |
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Sequential Logic Design Practices | |
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Sequential-Circuit Documentation Standards | |
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Latches and Flip-Flops | |
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Sequential PLDs | |
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Counters | |
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Shift Registers | |
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Iterative versus Sequential Circuits | |
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Synchronous Design Methodology | |
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Impediments to Synchronous Design | |
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Synchronizer Failure and Metastability | |
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Memory, CPLDs, and FPGAs | |
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Read-Only Memory | |
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Read/Write Memory | |
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Static RAM | |
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Dynamic RAM | |
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Complex Programmable Logic Devices | |
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Field-Programmable Gate Arrays | |
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Index | |