Art of Analog Layout

ISBN-10: 0130870617

ISBN-13: 9780130870612

Edition: 2001

List price: $112.00
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For courses in Analog Layout. The first textbook in the field. This text provides students with a broad understanding of the issues involved in successfully laying out analog integrated circuitsranging from the mechanics of layout to essential information about many related areas, such as device physics, processing, failure modes and effects, device operation, parasitics, and matching. It emphasizes practical knowledge.
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Book details

List price: $112.00
Copyright year: 2001
Publisher: Prentice Hall PTR
Publication date: 10/18/2000
Binding: Hardcover
Pages: 539
Size: 8.25" wide x 10.25" long x 1.00" tall
Weight: 2.596
Language: English

Device Physics
Generation and Recombination
Extrinsic Semiconductors
Diffusion and Drift
PN Junctions
Depletion Regions
PH Diodes
Schottky Diodes
Zener Diodes
Ohmic Contacts
Bipolar Junction Transistors
I-V Characteristics
MOS Transistors
Threshold Voltage
I-V Characteristics
JFET Transistors
Semiconductor Fabrication
Silicon Manufacture
Crystal Growth
Wafer Manufacturing
The Crystal Structure of Silicon
Photomasks and Reticles
Oxide Growth and Removal
Oxide Growth and Deposition
Oxide Removal
Other Effects of Oxide Growth and Removal
Local Oxidation of Silicon (LOCOS)
Diffusion and Ion Implantation
Other Effects of Diffusion
Ion Implantation
Silicon Deposition
Polysilicon Deposition
Deposition and Removal of Aluminum
Refractory Barrier Metal
Interlevel Oxide, Interlevel Nitride, and Protective Overcoat
Mount and Bond
Representative Processes
Standard Bipolar
Essential Features
Fabrication Sequence
Available Devices
Process Extensions
Polysilicon-Gate CMOS
Essential Features
Fabrication Sequence
Available Devices
Process Extensions
Analog BiCMOS
Essential Features
Fabrication Sequence
Available Devices
Process Extensions
Failure Mechanisms
Electrical Overstress
Electrostatic Discharge (ESD)
The Antenna Effect
Dry Corrosion
Mobile Ion Contamination
Surface Effects
Hot Carrier Injection
Parasitic Channels and Charge Spreading
Substrate Debiasing
Minority-Carrier Injection
Resistivity and Sheet Resistance
Resistor Layout
Resistor Variability
Process Variation
Temperature Variation
Contact Resistance
Resistor Parasitics
Comparison of Available Resistors
Base Resistors
Emitter Resistors
Base Pinch Resistors
High-Sheet Resistors
Epi Pinch Resistors
Metal Resistors
Poly Resistors
NSD and PSD Resistors
N-Well Resistors
Thin-Film Resistors
Adjusting Resistor Values
Tweaking Resistors
Trimming Resistors
Capacitor Variability
Process Variation
Voltage Modulation and Temperature Variation
Capacitor Parasitics
Comparison of Available Capacitors
Base-Emitter Junction Capacitors
MOS Capacitors
Poly-Poly Capacitors
Miscellaneous Styles of Capacitors
Matching of Resistors and Capacitors
Measuring Mismatch
Causes of Mismatch
Random Statistical Fluctuations
Process Biases
Pattern Shift
Variations in Polysilicon Etch Rate
Diffusion Interactions
Stress Gradients and Package Shifts
Temperature Gradients and Thermoelectrics
Electrostatic Interactions
Rules for Device Matching
Rules for Resistor Matching
Rules for Capacitor Matching
Bipolar Transistors
Topics in Bipolar Transistor Operation
Beta Rolloff
Avalanche Breakdown
Thermal Runaway and Secondary Breakdown
Saturation in NPN Transistors
Saturation in Lateral PNP Transistors
Parasitics of Bipolar Transistors
Standard Bipolar Small-Signal
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