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Introductory Concepts | |
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Numerical Representations | |
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Digital and Analog Systems | |
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Digital Number Systems | |
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Representing Binary Quantities | |
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Digital Circuits/Logic Circuits | |
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Parallel and Series Transmission | |
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Memory | |
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Digital Computers | |
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Number Systems and Codes | |
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Binary-to-Decimal Conversions | |
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Decimal-to-Binary Conversions | |
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Octal Number System | |
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Hexadecimal Number System | |
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BCD Code | |
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Putting It All Together | |
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The Byte, Nibble, and Word | |
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Alphanumeric Codes | |
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Parity Method for Error Detection | |
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Applications | |
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Describing Logic Circuits | |
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Boolean Constants and Variables | |
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Truth Tables | |
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OR Operation with OR Gates | |
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AND Operation with AND Gates | |
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NOT Operation | |
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Describing Logic Circuits Algebraically | |
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Evaluating Logic-Circuit Outputs | |
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Implementing Circuits from Boolean Expressions | |
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NOR Gates and NAND Gates | |
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Boolean Theorems | |
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DeMorgan's Theorems | |
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Universality of NAND Gates and NOR Gates | |
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Alternate Logic-Gate Representations | |
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Which Gate Representation to Use | |
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IEEE/ANSI Standard Logic Symbols | |
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Summary of Methods to Describe Logic Circuits | |
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Description Languages Versus Programming Languages | |
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Implementing Logic Circuits with PLDs | |
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HDL Format and Syntax | |
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Intermediate Signals | |
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Combinational Logic Circuits | |
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Sum-of-Products Form | |
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Simplifying Logic Circuits | |
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Algebraic Simplification | |
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Designing Combinational Logic Circuits | |
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Karnaugh Map Method | |
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Exclusive-OR and Exclusive-NOR Circuits | |
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Parity Generator and Checker | |
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Enable/Disable Circuits | |
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Basic Characteristics of Digital ICs | |
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Troubleshooting Digital Systems | |
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Internal Digital IC Faults | |
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External Faults | |
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Troubleshooting Case Study | |
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Programmable Logic Devices | |
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Representing Data in HDL | |
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Truth Tables Using HDL | |
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Decision Control Structures in HDL | |
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Flip-Flops and Related Devices | |
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NAND Gate Latch | |
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NOR Gate Latch | |
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Troubleshooting Case Study | |
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Clock Signals and Clocked Flip-Flops | |
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Clocked S-C Flip-Flop | |
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Clocked J-K Flip-Flop | |
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Clocked D Flip-Flop | |
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D Latch (Transparent Latch) | |
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Asynchronous Inputs | |
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IEEE/ANSI Symbols | |
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Flip-Flop Timing Considerations | |
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Potential Timing Problem in FF Circuits | |
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Master/Slave Flip-Flops | |
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Flip-Flop Applications | |
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Flip-Flop Synchronization | |
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Detecting an Input Sequence | |
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Data Storage and Transfer | |
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Serial Data Transfer: Shift Registers | |
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Frequency Division and Counting | |
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Microcomputer Application | |
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Schmitt-Trigger Devices | |
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One-Shot (Monostable Multivibrator) | |
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Analyzing Sequential Circuits | |
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Clock Generator Circuits | |
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Troubleshooting Flip-Flop Circuits | |
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Sequential Circuits Using HDL | |
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Edge-Triggered Devices | |
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HDL Circuits with Multiple Components | |
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Digital Arithmetic: Operations and Circuits | |
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Binary Addition | |
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Representing Signed Numbers | |
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Addition in the 2's-Complement System | |
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Subtraction in the 2's-Complement System | |
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Multiplication of Binary Numbers | |
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Binary Division | |
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BCD Addition | |
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Hexadecimal Arithmetic | |
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Arithmetic Circuits | |
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Parallel Binary Adder | |
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Design of a Full Adder | |
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Complete Parallel Adder with Registers | |
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Carry Propagation | |
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Integrated-Circuit Parallel Adder | |
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2's-Complement System | |
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BCD Adder | |
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ALU Integrated Circuits | |
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IEEE/ANSI Symbols | |
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Troubleshooting Case Study | |
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Using TTL Library Functions with HDL | |
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Logical Operations on Bit Arrays | |
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HDL Adders | |
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Expanding the Bit Capacity of a Circuit | |
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Counters and Registers | |
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Part I | |
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Asynchronous (Ripple) Counters | |
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Counters with MOD Numbers <2 N | |
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IC Asynchronous Counters | |
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Asynchronous Down Counter | |
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Propagation Delay in Ripple Counters | |
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Synchronous (Parallel) Counters | |
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Synchronous Down and Up/Down Counters | |
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Presettable Counters | |
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The 74LS193/HC193 | |
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More on the IEEE/ANSI Dependency Notation | |
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Decoding a Counter | |
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Decoding Glitches | |
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Cascading BCD Counters | |
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Synchronous Counter Design | |
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Basic Counters Using HDL | |
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Full Featured Counters in HDL | |
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LPM Counters | |
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State Machines | |
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Part II | |
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Integrated-Circuit Registers | |
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Parallel In/Parallel Out The 74ALS174/74HC174 | |
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Serial In/Serial Out The 4731B | |
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Parallel In/Serial Out The 74ALS165/74HC165 | |
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Serial In/Parallel Out The 74ALS164/74HC164 | |
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IEEE/ANSI Register Symbols | |
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Shift Register Counters | |
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Troubleshooting | |
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HDL Registers | |
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HDL Ring Counters | |
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HDL One-Shots | |
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Integrated-Circuit Logic Families | |
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Digital IC Terminology | |
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The TTL Logic Family | |
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TTL Data Sheets | |
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TTL Series Characteristics | |
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TTL Loading and Fan-Out | |
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Other TTL Characteristics | |
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MOS Technology | |
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Digital MOSFET Circuits | |
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Complementary MOS Logic | |
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CMOS Series Characteristics | |
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Low-Voltage Technology | |
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Open- Collector/Open-Drain Outputs | |
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Tristate (Three-State) Logic Outputs | |
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High-Speed Bus Interface Logic | |
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The ECL Digital IC Family | |
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CMOS Transmission Gate (Bilateral Switch) | |
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IC Interfacing | |
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TTL Driving CMOS | |
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CMOS Driving TTL | |
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Analog Voltage Comparators | |
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Troubleshooting | |
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MSI Logic Circuits | |
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Decoders | |
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BCD-to-7-Segment Decoder/Drivers | |
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Liquid-Crystal Displays | |
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Encoders | |
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Troubleshooting | |
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Multiplexers (Data Selectors) | |
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Multiplexer Applications | |
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Demultiplexers (Data Distributors) | |
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More Troubleshooting | |
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Magnitude Comparator | |
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Code Converters | |
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Data Busing | |
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The 74ALS173/HC173 Tristate Register | |
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Data Bus Operation | |
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Decoders Using HDL | |
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The HDL 7-Segment Decoder/Driver | |
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Encoders Using HDL | |
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HDL Multiplexers and Demultiplexers | |
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HDL Magnitude Comparators | |
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HDL Code Converters | |
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Digital System Projects Using HDL | |
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Small Project Management | |
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Stepper Motor Driver Project | |
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Keypad Encoder Project | |
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Digital Clock Project | |
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Frequency Counter Project | |
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Interfacing with the Analog World | |
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Review of Digital Versus Analog | |
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Digital-to-Analog Conversion | |
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D/A-Converter Circuitry | |
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DAC Specifications | |
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An Integrated-Circuit DAC | |
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DAC Applications | |
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Troubleshooting DACs | |
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Analog-to-Digital Conversion | |
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Digital-Ramp ADC | |
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Data Acquisition | |
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Successive-Approximation ADC | |
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Flash ADCs | |
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Other A/D Conversion Methods | |
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Digital Voltmeter | |
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Sample-and-Hold Circuits | |
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Multiplexing | |
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Digital Storage Oscilloscope | |
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Digital Signal Processing (DSP) | |
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Memory Devices | |
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Memory Terminology | |
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General Memory Operation | |
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CPU-Memory Connections | |
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Read-Only Memories | |
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ROM Architecture | |
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ROM Timing | |
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Types of ROMs | |
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Flash Memory | |
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ROM Applications | |
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Semiconductor RAM | |
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RAM Architecture | |
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Static RAM (SRAM) | |
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Dynamic RAM (DRAM) | |
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Dynamic RAM Structure and Operation | |
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DRAM Read/Write Cycles | |
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DRAM Refreshing | |
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DRAM Technology | |
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Expanding Word Size and Capacity | |
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Special Memory Functions | |
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Troubleshooting RAM Systems | |
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Testing ROM | |
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Programmable Logic Device Architectures | |
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Digital Systems Family Tree | |
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Fundamentals of PLD Circuitry | |
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PLD Architectures | |
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The GAL 16V8A (Generic Array Logic) | |
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The Altera EPM7128S CPLD | |
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The Altera FLEX10K Family | |
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Glossary | |
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Answers to Selected Problems | |
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Index of ICs | |
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Index | |