Verilog Designer's Library

Name: Verilog Designer's Library
Price: 23.35 USD
Availability: InStock
ISBN: 9780130811547

ISBN-10: 0130811548

ISBN-13: 9780130811547

Edition: 1999

Authors: Bob Zeidman

List price: $95.00

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Description:

Hardware description languages are becoming the design method of choice for electrical engineers when designing circuits within today's electrical components. This book offers a guide to working with one of the most popular of these languages, Verilog.

Book details

List price: $95.00
Copyright year: 1999
Publisher: Prentice Hall PTR
Publication date: 6/15/1999
Binding: Paperback
Pages: 432
Size: 7.50" wide x 9.75" long x 1.00" tall
Weight: 1.892
Language: English

Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI




Coding Techniques



General Coding Techniques


Code Structure


Comments


Do Not Use Disable Instructions



Behavioral Coding Techniques


Eliminate Periodic Instructions


Eliminate Event Order Dependencies



RTL Coding Techniques


Synchronous Design


Allowable Uses of Asynchronous Logic



Synthesis Issues


Correlated Unknown Signals


State Machines


Optimizing Out Terms


Always Blocks



Simulation Issues


Simulate The Corner Cases


Use Code Coverage Tools


Use The Triple Equals


Use The $display And $stop Statements



Basic Building Blocks



The J-K Flip Flop


Behavioral Code


RTL Code


Simulation Code



The Shift Register


Behavioral Code


RTL Code


Simulation Code



The Counter


Behavioral Code


RTL Code


Simulation Code



The Adder


Behavioral Code


RTL Code


Simulation Code



State Machines



The Moore State Machine


Behavioral Code


RTL Code


Simulation Code



The Mealy State Machine


Behavioral Code


RTL Code


Simulation Code



The One-Hot State Machine for FPGAs


RTL Code


Simulation Code



Miscellaneous Complex Functions



The Linear Feedback Shift Register (LFSR)


Behavioral Code


RTL Code


Simulation Code



The Encrypter/Decrypter


Behavioral Code


RTL Code


Simulation Code



The Phase Locked Loop (PLL)


Behavioral Code


RTL Code


Simulation Code



The Unsigned Integer Multiplier


Behavioral Code


RTL Code


Simulation Code



The Signed Integer Multiplier


Behavioral Code


RTL Code


Simulation Code



Error Detection and Correction



The Parity Generator and Checker


Implementation Code


Simulation Code



Hamming Code Logic


Implementation Code


Simulation Code



The Checksum


Implementation Code


Simulation Code



The Cyclic Redundancy Check (CRC)


Behavioral Code


RTL Code


Simulation Code



Memories



The Random Access Memory (RAM)


Implementation Code


Simulation Code



The Dual Port RAM


Implementation Code


Simulation Code



The Synchronous FIFO


Behavioral Code


RTL Code


Simulation Code



The Synchronizing FIFO


Behavioral Code


RTL Code


Simulation Code



Memory Controllers



The SRAM/ROM Controller


Behavioral Code


RTL Code


Simulation Code



The Synchronous SRAM Controller


Behavioral Code


RTL Code


Simulation Code



The DRAM Controller


Behavioral Code


RTL Code


Simulation Code



The Fast Page Mode DRAM Controller


Behavioral Code


RTL Code


Simulation Code



Resources


Glossary


Index