Network Processors Architecture, Programming, and Implementation

Name: Network Processors Architecture, Programming, and Implementation
Price: 24.85 USD
Availability: InStock
ISBN: 9780123708915

ISBN-10: 0123708915

ISBN-13: 9780123708915

Edition: 2008

Authors: Ran Giladi

List price: $103.00

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Description:

"Network processors are the basic building blocks in today's high-speed, high-demand, quality oriented communication networks. Designing and implementing network processors requires a new paradigm and an in-depth understanding of network processing requirements. This books leads the reader through the requirements and the underlying theory of networks, network processing, and network processors. It covers implementation of network processors, and includes the EZchip Microcode Development Environment so that readers can gain hands-on experience in writing high speed networking applications. By the end of the book, the reader will be able to write and test applications on a simulated network…

Book details

List price: $103.00
Copyright year: 2008
Publisher: Elsevier Science & Technology
Publication date: 8/29/2008
Binding: Hardcover
Pages: 736
Size: 7.50" wide x 9.25" long x 1.75" tall
Weight: 3.080
Language: English

Ran Giladi is an associate professor in the department of Communication Systems Engineering at Ben-Gurion University of the Negev, Beer Sheva; he founded the department and has headed it for several years. In addition, he has taught in the Electrical Engineering Department and the Business School at Tel-Aviv University. Dr. Giladi has also been a system programmer, an R&D manager, a VP of R&D, and founder and CEO of several data communication companies. He is involved in the Israeli high-tech industry, serves as a board member in several companies (among them EZchip Technologies, a leading vendor of network processors), and is currently a venture partner with DFJ-TFV. His research interests…



Preface



Introduction and Motivation



Network Processors Ecosystem



Communication Systems and Applications



Network Elements



Network Processors



Structure of This Book



Summary



Networks



Networking Fundamentals



Introduction



Networks Primer



Data Networking Models



Basic Network Technologies



Telecom Networks



Data Networks



Summary


Appendix A


Appendix B



Converged Networks



Introduction



From Telecom Networks to Data Networks



From Datacom to Telecom



Summary


Appendix A



Access and Home Networks



Access Networks



Home and Building Networks



Summary



Processing



Packet Processing



Introduction and Definitions



Ingress and Egress



Framing



Parsing and Classification



Search, Lookup, and Forwarding



Modification



Compression and Encryption



Queueing and Traffic Management



Summary



Packet Flow Handling



Definitions



Quality of Service



Class of Service



QoS Mechanisms



Summary



Architecture



Introduction



Background and Definitions



Equipment Design Alternatives:ASICs versus NP



Network Processors Basic Architectures



Instruction Set (Scalability; Processing Speed)



NP Components



Summary



Software



Introduction



Conventional Systems



Programming Models Classification



Parallel Programming



Pipelining



Network Processor Programming



Summary


Appendix A


Appendix B


Appendix C



NP Peripherals



Switch Fabrics



CoProcessors



Summary



A Network Processor: EZchip



EZchip Architecture, Capabilities, and Applications



General description



System Architecture



Lookup Structures



Counters, Statistics and Rate Control



Traffic Management



Stateful Classification



Multicast Frames



Data Flow



Summary



EZchip Programming



Instruction Pipeline



Writing NP Microcode



Preprocessor Overview



Developing and Running NP Applications



TOP Common Commands



Summary


Appendix A



Parsing



Internal Engine Diagram



TOPparse Registers



TOPparse Structures



TOPparse Instruction Set



Example



Summary


Appendix A


Appendix B


Appendix C



Searching



Introduction



Internal Engine Diagram



TOPsearch I Structures



Interface to TOPparse (Input to TOPsearch)



Interface to TOPresolve (Output of TOPsearch)



Hash Table Learning



Example



Summary



Resolving



Internal Engine Diagram



TOPresolve Registers



TOPresolve Structures



TOPresolve Instruction Set



Example



Summary


Appendix A


Appendix B


Appendix C



Modifying



Introduction



Internal Engine Diagram



TOPmodify Registers



TOPmodify Structures



TOPmodify Instruction Set



Example



Summary


Appendix A


Appendix B


Appendix C



Running the Virtual Local Area Network Example



Installation



Getting Started



Microcode Development Workflow



Summary



Writing Your First High-Speed Network Application



Introduction



Data Flow and TOP Microcode



Data Structures



Summary


List of Acronyms


References


Index