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| Foreword | |
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| Preface | |
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| Style and Limits | |
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| Conventions | |
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| Acknowledgments | |
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| RISCs and MIPS Architectures | |
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| Pipelines | |
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| What Makes a Pipeline Inefficient? | |
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| The Pipeline and Caching | |
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| The MIPS Five-Stage Pipeline | |
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| RISC and CISC | |
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| Great MIPS Chips of the Past and Present | |
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| R2000 to R3000 Processors | |
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| The R6000 Processor: A Diversion | |
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| The First CPU Cores | |
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| The R4000 Processor: A Revolution | |
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| The Rise and Fall of the ACE Consortium | |
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| SGI Acquires MIPS | |
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| QED: Fast MIPS Processors for Embedded Systems | |
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| The R10000 Processor and its Successors | |
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| MIPS Processors in Consumer Electronics | |
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| MIPS in Network Routers and Laser Printers | |
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| MIPS Processors in Modern Times | |
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| The Rebirth of MIPS Technologies | |
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| The Present Day | |
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| MIPS Compared with CISC Architectures | |
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| Constraints on MIPS Instructions | |
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| Addressing and Memory Accesses | |
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| Features You Won't Find | |
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| Programmer-Visible Pipeline Effects | |
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| MIPS Architecture | |
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| A Flavor of MIPS Assembly Language | |
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| Registers | |
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| Conventional Names and Uses of General-Purpose Registers | |
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| Integer Multiply Unit and Registers | |
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| Loading and Storing: Addressing Modes | |
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| Data Types in Memory and Registers | |
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| Integer Data Types | |
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| Unaligned Loads and Stores | |
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| Floating-Point Data in Memory | |
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| Synthesized Instructions in Assembly Language | |
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| MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions | |
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| To 64 Bits | |
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| Who Needs 64 Bits? | |
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| Regarding 64 Bits and No Mode Switch: Data in Registers | |
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| Basic Address Space | |
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| Addressing in Simple Systems | |
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| Kernel versus User Privilege Level | |
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| The Pull Picture: The 64-Bit View of the Memory Map | |
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| Pipeline Visibility | |
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| Coprocessor 0: MIPS Processor Control | |
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| CPU Control Instructions | |
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| Which Registers Are Relevant When? | |
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| CPU Control Registers and Their Encoding | |
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| Status Register (SR) | |
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| Cause Register | |
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| Exception Restart Address (EPC) Register | |
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| Bad Virtual Address (BadVAddr) Register | |
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| Count/Compare Registers: The On-CPU Timer | |
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| Processor ID (PRId) Register | |
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| Config Registers: CPU Resource Information and Configuration | |
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| EBase and IntCtl: Interrupt and Exception Setup | |
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| SRSCtl and SRSMap: Shadow Register Setup | |
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| Load-Linked Address (LLAddr) Register | |
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| CP0 Hazards-A Trap for the Unwary | |
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| Hazard Barrier Instructions | |
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| Instruction Hazards and User Hazards | |
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| Hazards between CP0 Instructions | |
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| How Caches Work on MIPS Processors | |
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| Caches and Cache Management | |
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| How Caches Work | |
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| Write-Through Caches in Early MIPS CPUs | |
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| Write-Back Caches in MIPS CPUs | |
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| Other Choices in Cache Design | |
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| Managing Caches | |
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| L2 and L3 Caches | |
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| Cache Configurations for MIPS CPUs | |
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| Programming MIPS32/64 Caches | |
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| The Cache Instruction | |
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| Cache Initialization and Tag/Data Registers | |
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| CacheErr, ERR, and ErrorEPC Registers: Memory/Cache Error Handling | |
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| Cache Sizing and Figuring Out Configuration | |
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| Initialization Routines | |
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| Invalidating or Writing Back a Region of Memory in the Cache | |
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| Cache Efficiency | |
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| Reorganizing Software to Influence Cache Efficiency | |
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| Cache Aliases | |
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| Exceptions, Interrupts, and Initialization | |
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| Precise Exceptions | |
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| Nonprecise Exceptions-The Multiplier in Historic MIPS CPUs | |
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| When Exceptions Happen | |
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| Exception Vectors: Where Exception Handling Starts | |
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| Exception Handling: Basics | |
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| Returning from an Exception | |
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| Nesting Exceptions | |
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| An Exception Routine | |
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| Interrupts | |
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| Interrupt Resources in MIPS CPUs | |
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| Implementing Interrupt Priority in Software | |
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| Atomicity and Atomic Changes to SR | |
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| Critical Regions with Interrupts Enabled: Semaphores the MIPS Way | |
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| Vectored and EIC Interrupts in MIPS32/64 CPUs | |
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| Shadow Registers | |
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| Starting Up | |
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| Probing and Recognizing Your CPU | |
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| Bootstrap Sequences | |
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| Starting Up an Application | |
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| Emulating Instructions | |
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| Low-level Memory Management and the TLB | |
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| The TLB/MMU Hardware and What It Does | |
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| TLB/MMU Registers Described | |
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| TLB Key Fields-EntryHi and PageMask | |
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| TLB Output Fields-EntryLoO-1 | |
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| Selecting a TLB Entry-Index, Random, and Wired Registers | |
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| Page-Table Access Helpers-Context and XContext | |
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| TLB/MMU Control Instructions | |
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| Programming the TLB | |
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| How Refill Happens | |
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| Using ASIDs | |
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| The Random Register and Wired Entries | |
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| Hardware-Friendly Page Tables and Refill Mechanism | |
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| TLB Miss Handling | |
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| XTLB Miss Handler | |
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| Everyday Use of the MIPS TLB | |
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| Memory Management in a Simpler OS | |
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| Floating-Point Support | |
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| A Basic Description of Floating Point | |
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| The IEEE 754 Standard and Its Background | |
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| How IEEE Floating-Point Numbers Are Stored | |
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| IEEE Mantissa and Normalization | |
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| Reserved Exponent Values for Use with Strange Values | |
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| MIPS FP Data Formats | |
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| MIPS Implementation of IEEE 754 | |
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| Need for FP Trap Handler and Emulator in All MIPS CPUs | |
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| Floating-Point Registers | |
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| Conventional Names and Uses of Floating-Point Registers | |
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| Floating-Point Exceptions/Interrupts | |
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| Floating-Point Control: The Control/Status Register | |
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| Floating-Point Implementation Register | |
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| Guide to FP Instructions | |
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| Load/Store | |
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| Move between Registers | |
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| Three-Operand Arithmetic Operations | |
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| Multiply-Add Operations | |
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| Unary (Sign-Changing) Operations | |
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| Conversion Operations | |
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| Conditional Branch and Test Instructions | |
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| Paired-Single Floating-Point Instructions and the MIPS-3D ASE | |
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| Exceptions on Paired-Single Instructions | |
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| Paired-Single Three-Operand Arithmetic, Multiply-Add, Sign-Changing, and Nonconditional Move Operations | |
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| Paired-Single Conversion Operations | |
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| Paired-Single Test and Conditional Move Instructions | |
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| MIPS-3D Instructions | |
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| Instruction Timing Requirements | |
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| Instruction Timing for Speed | |
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| Initialization and Enabling on Demand | |
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| Floating-Point Emulation | |
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| Complete Guide to the MIPS Instruction Set | |
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| A Simple Example | |
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| Assembly Instructions and What They Mean | |
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| U and Non-U Mnemonics | |
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| Divide Mnemonics | |
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| Inventory of Instructions | |
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| Floating-Point Instructions | |
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| Differences in MIPS32/64 Release 1 | |
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| Regular Instructions Added in Release 2 | |
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| Privileged Instructions Added in Release 2 | |
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| Peculiar Instructions and Their Purposes | |
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| Load Left/Load Right: Unaligned Load and Store | |
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| Load-Linked/Store-Conditional | |
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| Conditional Move Instructions | |
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| Branch-Likely | |
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| Integer Multiply-Accumulate and Multiply-Add Instructions | |
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| Floating-Point Multiply-Add Instructions | |
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| Multiple FP Condition Bits | |
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| Prefetch | |
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| Sync: A Memory Barrier for Loads and Stores | |
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| Hazard Barrier Instructions | |
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| Synci: Cache Management for Instruction Writers | |
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| Read Hardware Register | |
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| Instruction Encodings | |
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| Fields in the Instruction Encoding Table | |
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| Notes on the Instruction Encoding Table | |
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| Encodings and Simple Implementation | |
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| Instructions by Functional Group | |
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| No-op | |
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| Register/Register Moves | |
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| Load Constant | |
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| Arithmetical/Logical | |
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| Integer Multiply, Divide, and Remainder | |
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| Integer Multiply-Accumulate | |
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| Loads and Stores | |
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| Jumps, Subroutine Calls, and Branches | |
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| Breakpoint and Trap | |
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| CP0 Functions | |
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| Floating Point | |
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| Limited User-Mode Access to "Under the Hood" Features | |
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| Reading MIPS Assembly Language | |
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| A Simple Example | |
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| Syntax Overview | |
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| Layout, Delimiters, and Identifiers | |
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| General Rules for Instructions | |
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| Computational Instructions: Three-, Two-, and One-Register | |
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| Immediates: Computational Instructions with Constants | |
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| Regarding 64-Bit and 32-Bit Instructions | |
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| Addressing Modes | |
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| Gp-Relative Addressing | |
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| Object File and Memory Layout | |
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| Practical Program Layout, Including Stack and Heap | |
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| Porting Software to the MIPS Architecture | |
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| Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems | |
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| Endianness: Words, Bytes, and Bit Order | |
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| Bits, Bytes, Words, and Integers | |
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| Software and Endianness | |
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| Hardware and Endianness | |
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| Bi-endian Software for a MIPS CPU | |
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| Portability and Endianness-Independent Code | |
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| Endianness and Foreign Data | |
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| Trouble with Visible Caches | |
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| Cache Management and DMA Data | |
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| Cache Management and Writing Instructions: Self-Modifying Code | |
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| Cache Management and Uncached or Write-Through Data | |
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| Cache Aliases and Page Coloring | |
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| Memory Access Ordering and Reordering | |
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| Ordering and Write Buffers | |
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| Implementing wbflush | |
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| Writing it in C | |
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| Wrapping Assembly Code with the GNU C Compiler | |
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| Memory-Mapped I/O Registers and "Volatile" | |
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| Miscellaneous Issues When Writing C for MIPS Applications | |
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| MIPS Software Standards (ABIs) | |
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| Data Representations and Alignment | |
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| Sizes of Basic Types | |
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| Sizes of "long" and Pointer Types | |
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| Alignment Requirements | |
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| Memory Layout of Basic Types and How It Changes with Endianness | |
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| Memory Layout of Structure and Array Types and Alignment | |
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| Bitfields in Structures | |
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| Unaligned Data from C | |
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| Argument Passing and Stack Conventions for MIPS ABIs | |
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| The Stack, Subroutine Linkage, and Parameter Passing | |
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| Stack Argument Structure in o32 | |
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| Using Registers to Pass Arguments | |
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| Examples from the C Library | |
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| An Exotic Example: Passing Structures | |
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| Passing a Variable Number of Arguments | |
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| Returning a Value from a Function | |
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| Evolving Register-Use Standards: SGIs n32 and n64 | |
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| Stack Layouts, Stack Frames, and Helping Debuggers | |
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| Variable Number of Arguments and stdargs | |
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| Debugging MIPS Designs-Debug and Profiling Features | |
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| The "EJTAG" On-chip Debug Unit | |
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| EJTAG History | |
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| How the Probe Controls the CPU | |
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| Debug Communications through JTAG | |
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| Debug Mode | |
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| Single-Stepping | |
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| The dseg Memory Decode Region | |
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| EJTAG CP0 Registers, Particularly Debug | |
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| The DCR (Debug Control) Memory-Mapped Register | |
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| EJTAG Breakpoint Hardware | |
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| Understanding Breakpoint Conditions | |
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| Imprecise Debug Breaks | |
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| PC Sampling with EJTAG | |
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| Using EJTAG without a Probe | |
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| Pre-EJTAG Debug Support-Break Instruction and CP0 Watchpoints | |
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| PDtrace | |
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| Performance Counters | |
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| GNU/Linux from Eight Miles High | |
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| Components | |
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| Layering in the Kernel | |
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| MIPS CPU in Exception Mode | |
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| MIPS CPU with Some or All Interrupts off | |
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| Interrupt Context | |
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| Executing the Kernel in Thread Context | |
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| How Hardware and Software Work Together | |
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| The Life and Times of an Interrupt | |
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| High-Performance Interrupt Handling and Linux | |
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| Threads, Critical Regions, and Atomicity | |
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| MIPS Architecture and Atomic Operations | |
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| Linux Spinlocks | |
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| What Happens on a System Call | |
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| How Addresses Get Translated in Linux/MIPS Systems | |
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| What's Memory Translation For? | |
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| Basic Process Layout and Protection | |
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| Mapping Process Addresses to Real Memory | |
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| Paged Mapping Preferred | |
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| What We Really Want | |
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| Origins of the MIPS Design | |
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| Keeping Track of Modified Pages (Simulating "Dirty" Bits) | |
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| How the Kernel Services a TLB Refill Exception | |
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| Care and Maintenance of the TLB | |
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| Memory Translation and 64-Bit Pointers | |
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| MIPS Specific Issues in the Linux Kernel | |
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| Explicit Cache Management | |
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| DMA Device Accesses | |
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| Writing Instructions for Later Execution | |
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| Cache/Memory Mapping Problems | |
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| Cache Aliases | |
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| CP0 Pipeline Hazards | |
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| Multiprocessor Systems and Coherent Caches | |
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| Demon Tweaks for a Critical Routine | |
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| Linux Application Code, PIC, and Libraries | |
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| How Link Units Get into a Program | |
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| Global Offset Table (GOT) Organization | |
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| MIPS Multithreading | |
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| What Is Multithreading? | |
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| Why Is MT Useful? | |
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| How to Do Multithreading for MIPS | |
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| MT in Action | |
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| Other Optional Extensions to the MIPS Instruction Set | |
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| MIPS16 and MIPS16e ASEs | |
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| Special Encodings and Instructions in the MIPS16 ASE | |
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| The MIPS16 ASE Evaluated | |
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| The MIPS DSP ASE | |
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| The MDMX ASE | |
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| MIPS Glossary | |
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| References | |
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| Books and Articles | |
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| Online Resources | |
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| Index | |