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Analysis and Design of Digital Integrated Circuits

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ISBN-10: 0072283653

ISBN-13: 9780072283655

Edition: 3rd 2004 (Revised)

Authors: David A. Hodges, Horace G. Jackson, Resve A. Saleh

List price: $213.13
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Book details

List price: $213.13
Edition: 3rd
Copyright year: 2004
Publisher: McGraw-Hill Higher Education
Publication date: 7/18/2003
Binding: Hardcover
Pages: 600
Size: 7.25" wide x 9.25" long x 1.00" tall
Weight: 2.398
Language: English

Preface to Third Edition
Deep Submicron Digital IC Design
Brief History of IC Industry
Review of Digital Logic Gate Design
Basic Logic Functions
Implementation of Logic Circuits
Definition of Noise Margin
Definition of Transient Characteristics
Power Estimation
Digital Integrated Circuit Design
MOS Transistor Structure and Operation
Deep Submicron Interconnect
Computer-Aided Design of Digital Circuits
Circuit Simulation and Analysis
The Challenges Ahead
MOS Transistors
Structure and Operation of the MOS Transistor
Threshold Voltage of the MOS Transistor
First-Order Current-Voltage Characteristics
Derivation of Velocity-Saturated Current Equations
Effect of High Fields
Current Equations for Velocity-Saturated Devices
Alpha-Power Law Model
Subthreshold Conduction
Capacitances of the MOS Transistor
Thin-Oxide Capacitance
pn Junction Capacitance
Overlap Capacitance
Fabrication, Layout, and Simulation
IC Fabrication Technology
Overview of IC Fabrication Process
IC Photolithographic Process
Making Transistors
Making Wires
Wire Capacitance and Resistance
Layout Basics
Modeling the MOS Transistor for Circuit Simulation
MOS Models in SPICE
Specifying MOS Transistors
SPICE MOS LEVEL 1 Device Model
Extraction of Parameters for MOS LEVEL 1
BSIM3 Model
Binning Process in BSIM3
Short-Channel Threshold Voltage
Mobility Model
Linear and Saturation Regions
Subthreshold Current
Capacitance Models
Source/Drain Resistance
Additional Effects in MOS Transistors
Parameter Variations in Production
Temperature Effects
Supply Variations
Voltage Limitations
CMOS Latch-up
Silicon-on-Insulator (SOI) Technology
SPICE Model Summary
MOS Inverter Circuits
Voltage Transfer Characteristics
Noise Margin Definitions
Single-Source Noise Margin (SSNM)
Multiple-Source Noise Margin (MSNM)
Resistive-Load Inverter Design
NMOS Transistors as Load Devices
Saturated Enhancement Load
Linear Enhancement Load
Complementary MOS (CMOS) Inverters
DC Analysis of CMOS Inverter
Layout Design of CMOS Inverter
Pseudo-NMOS Inverters
Sizing Inverters
Tristate Inverters
Static MOS Gate Circuits
CMOS Gate Circuits
Basic CMOS Gate Sizing
Fanin and Fanout Considerations
Voltage Transfer Characteristics (VTC) of CMOS Gates
Complex CMOS Gates
XOR and XNOR Gates
Multiplexer Circuits
Flip-Flops and Latches
Basic Bistable Circuit
SR Latch
JK Flip-Flop
JK Master-Slave Flip-Flop
JK Edge-Triggered Flip-Flop
D Flip-Flops and Latches
Power Dissipation in CMOS Gates
Dynamic (Switching) Power
Static (Standby) Power
Complete Power Equation
Power and Delay Tradeoffs
High-Speed CMOS Logic Design
Switching Time Analysis
Gate Sizing Revisited--Velocity Saturation Effects
Detailed Load Capacitance Calculation
Fanout Gate Capacitance
Self-Capacitance Calculation
Wire Capacitance
Improving Delay Calculation with Input Slope
Gate Sizing for Optimal Path Delay
Optimal Delay Problem
Inverter Chain Delay Optimization--FO4 Delay
Optimizing Paths with NANDs and NORs
Optimizing Paths with Logical Effort
Derivation of Logical Effort
Understanding Logical Effort
Branching Effort and Sideloads
Transfer Gate and Dynamic Logic Design
Basic Concepts
Pass Transistors
Capacitive Feedthrough
Charge Sharing
Other Sources of Charge Loss
CMOS Transmission Gate Logic
Multiplexers Using CMOS Transfer Gates
CMOS Transmission Gate Delays
Logical Effort with CMOS Transmission Gates
Dynamic D-Latches and D Flip-Flops
Domino Logic
Logical Effort for Domino Gates
Limitations of Domino Logic
Dual-Rail (Differential) Domino Logic
Self-Resetting Circuits
Semiconductor Memory Design
Memory Organization
Types of Memory
Memory Timing Parameters
MOS Decoders
Static RAM Cell Design
Static Memory Operation
Read Operation
Write Operation
SRAM Cell Layout
SRAM Column I/O Circuitry
Column Pull-Ups
Column Selection
Write Circuitry
Read Circuitry
Memory Architecture
Additional Topics in Memory Design
Content-Addressable Memories (CAMs)
Field-Programmable Gate Array
Dynamic Read-Write Memories
Three-Transistor Dynamic Cell
One-Transistor Dynamic Cell
External Characteristics of Dynamic RAMs
Read-Only Memories
MOS ROM Cell Arrays
EPROMs and E[superscript 2]PROMs
Flash Memory
Interconnect Design
Interconnect RC Delays
Wire Resistance
Elmore Delay Calculation
RC Delay in Long Wires
Buffer Insertion for Very Long Wires
Interconnect Coupling Capacitance
Components of Coupling Capacitance
Coupling Effects on Delay
Capacitive Noise or Crosstalk
Interconnect Inductance
Antenna Effects
Power Grid and Clock Design
Power Distribution Design
IR Drop and Ldi/dt
Power Routing Considerations
Decoupling Capacitance Design
Power Distribution Design Example
Clocking and Timing Issues
Clock Definitions and Metrics
Clock Skew
Effect of Noise on Clocks and FFs
Power Dissipation in Clocks
Clock Generation
Clock Distribution for High-Performance Designs
Example of a Clock Distribution Network
Phase-Locked Loops/Delay-Locked Loops
PLL Design Considerations
Clock Distribution Summary
A Brief Introduction to SPICE
Design Flow
Settings of Various Global Parameters
Listing of Sources and Active and Passive Elements
Analysis Statements
Complete SPICE Examples
Bipolar Transistors and Circuits
The Bipolar Junction Transistor
The Schottky-Barrier Diode
BJT Model for Circuit Simulation
Bipolar Transistor Inverter
Voltage Transfer Characteristics
Schottky-Clamped Inverter
BJT Inverter Switching Times
Bipolar Digital Gate Circuits
Voltage Transfer Characteristics
Propagation Delay Time
Input Clamp Diodes