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| Preface to Third Edition | |
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| Deep Submicron Digital IC Design | |
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| Introduction | |
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| Brief History of IC Industry | |
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| Review of Digital Logic Gate Design | |
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| Basic Logic Functions | |
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| Implementation of Logic Circuits | |
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| Definition of Noise Margin | |
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| Definition of Transient Characteristics | |
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| Power Estimation | |
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| Digital Integrated Circuit Design | |
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| MOS Transistor Structure and Operation | |
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| CMOS Versus NMOS | |
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| Deep Submicron Interconnect | |
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| Computer-Aided Design of Digital Circuits | |
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| Circuit Simulation and Analysis | |
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| The Challenges Ahead | |
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| Summary | |
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| MOS Transistors | |
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| Introduction | |
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| Structure and Operation of the MOS Transistor | |
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| Threshold Voltage of the MOS Transistor | |
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| First-Order Current-Voltage Characteristics | |
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| Derivation of Velocity-Saturated Current Equations | |
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| Effect of High Fields | |
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| Current Equations for Velocity-Saturated Devices | |
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| Alpha-Power Law Model | |
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| Subthreshold Conduction | |
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| Capacitances of the MOS Transistor | |
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| Thin-Oxide Capacitance | |
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| pn Junction Capacitance | |
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| Overlap Capacitance | |
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| Summary | |
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| Fabrication, Layout, and Simulation | |
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| Introduction | |
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| IC Fabrication Technology | |
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| Overview of IC Fabrication Process | |
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| IC Photolithographic Process | |
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| Making Transistors | |
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| Making Wires | |
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| Wire Capacitance and Resistance | |
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| Layout Basics | |
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| Modeling the MOS Transistor for Circuit Simulation | |
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| MOS Models in SPICE | |
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| Specifying MOS Transistors | |
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| SPICE MOS LEVEL 1 Device Model | |
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| Extraction of Parameters for MOS LEVEL 1 | |
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| BSIM3 Model | |
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| Binning Process in BSIM3 | |
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| Short-Channel Threshold Voltage | |
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| Mobility Model | |
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| Linear and Saturation Regions | |
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| Subthreshold Current | |
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| Capacitance Models | |
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| Source/Drain Resistance | |
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| Additional Effects in MOS Transistors | |
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| Parameter Variations in Production | |
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| Temperature Effects | |
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| Supply Variations | |
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| Voltage Limitations | |
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| CMOS Latch-up | |
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| Silicon-on-Insulator (SOI) Technology | |
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| SPICE Model Summary | |
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| MOS Inverter Circuits | |
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| Introduction | |
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| Voltage Transfer Characteristics | |
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| Noise Margin Definitions | |
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| Single-Source Noise Margin (SSNM) | |
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| Multiple-Source Noise Margin (MSNM) | |
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| Resistive-Load Inverter Design | |
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| NMOS Transistors as Load Devices | |
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| Saturated Enhancement Load | |
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| Linear Enhancement Load | |
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| Complementary MOS (CMOS) Inverters | |
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| DC Analysis of CMOS Inverter | |
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| Layout Design of CMOS Inverter | |
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| Pseudo-NMOS Inverters | |
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| Sizing Inverters | |
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| Tristate Inverters | |
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| Summary | |
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| Static MOS Gate Circuits | |
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| Introduction | |
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| CMOS Gate Circuits | |
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| Basic CMOS Gate Sizing | |
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| Fanin and Fanout Considerations | |
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| Voltage Transfer Characteristics (VTC) of CMOS Gates | |
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| Complex CMOS Gates | |
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| XOR and XNOR Gates | |
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| Multiplexer Circuits | |
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| Flip-Flops and Latches | |
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| Basic Bistable Circuit | |
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| SR Latch | |
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| JK Flip-Flop | |
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| JK Master-Slave Flip-Flop | |
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| JK Edge-Triggered Flip-Flop | |
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| D Flip-Flops and Latches | |
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| Power Dissipation in CMOS Gates | |
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| Dynamic (Switching) Power | |
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| Static (Standby) Power | |
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| Complete Power Equation | |
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| Power and Delay Tradeoffs | |
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| Summary | |
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| High-Speed CMOS Logic Design | |
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| Introduction | |
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| Switching Time Analysis | |
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| Gate Sizing Revisited--Velocity Saturation Effects | |
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| Detailed Load Capacitance Calculation | |
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| Fanout Gate Capacitance | |
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| Self-Capacitance Calculation | |
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| Wire Capacitance | |
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| Improving Delay Calculation with Input Slope | |
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| Gate Sizing for Optimal Path Delay | |
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| Optimal Delay Problem | |
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| Inverter Chain Delay Optimization--FO4 Delay | |
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| Optimizing Paths with NANDs and NORs | |
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| Optimizing Paths with Logical Effort | |
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| Derivation of Logical Effort | |
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| Understanding Logical Effort | |
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| Branching Effort and Sideloads | |
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| Summary | |
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| Transfer Gate and Dynamic Logic Design | |
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| Introduction | |
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| Basic Concepts | |
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| Pass Transistors | |
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| Capacitive Feedthrough | |
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| Charge Sharing | |
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| Other Sources of Charge Loss | |
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| CMOS Transmission Gate Logic | |
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| Multiplexers Using CMOS Transfer Gates | |
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| CMOS Transmission Gate Delays | |
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| Logical Effort with CMOS Transmission Gates | |
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| Dynamic D-Latches and D Flip-Flops | |
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| Domino Logic | |
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| Logical Effort for Domino Gates | |
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| Limitations of Domino Logic | |
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| Dual-Rail (Differential) Domino Logic | |
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| Self-Resetting Circuits | |
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| Summary | |
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| Semiconductor Memory Design | |
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| Introduction | |
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| Memory Organization | |
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| Types of Memory | |
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| Memory Timing Parameters | |
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| MOS Decoders | |
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| Static RAM Cell Design | |
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| Static Memory Operation | |
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| Read Operation | |
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| Write Operation | |
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| SRAM Cell Layout | |
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| SRAM Column I/O Circuitry | |
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| Column Pull-Ups | |
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| Column Selection | |
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| Write Circuitry | |
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| Read Circuitry | |
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| Memory Architecture | |
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| Summary | |
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| Additional Topics in Memory Design | |
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| Introduction | |
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| Content-Addressable Memories (CAMs) | |
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| Field-Programmable Gate Array | |
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| Dynamic Read-Write Memories | |
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| Three-Transistor Dynamic Cell | |
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| One-Transistor Dynamic Cell | |
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| External Characteristics of Dynamic RAMs | |
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| Read-Only Memories | |
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| MOS ROM Cell Arrays | |
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| EPROMs and E[superscript 2]PROMs | |
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| Flash Memory | |
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| FRAMs | |
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| Summary | |
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| Interconnect Design | |
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| Introduction | |
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| Interconnect RC Delays | |
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| Wire Resistance | |
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| Elmore Delay Calculation | |
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| RC Delay in Long Wires | |
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| Buffer Insertion for Very Long Wires | |
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| Interconnect Coupling Capacitance | |
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| Components of Coupling Capacitance | |
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| Coupling Effects on Delay | |
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| Capacitive Noise or Crosstalk | |
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| Interconnect Inductance | |
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| Antenna Effects | |
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| Summary | |
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| Power Grid and Clock Design | |
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| Introduction | |
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| Power Distribution Design | |
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| IR Drop and Ldi/dt | |
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| Electromigration | |
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| Power Routing Considerations | |
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| Decoupling Capacitance Design | |
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| Power Distribution Design Example | |
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| Clocking and Timing Issues | |
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| Clock Definitions and Metrics | |
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| Clock Skew | |
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| Effect of Noise on Clocks and FFs | |
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| Power Dissipation in Clocks | |
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| Clock Generation | |
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| Clock Distribution for High-Performance Designs | |
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| Example of a Clock Distribution Network | |
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| Phase-Locked Loops/Delay-Locked Loops | |
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| PLL Design Considerations | |
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| Clock Distribution Summary | |
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| A Brief Introduction to SPICE | |
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| Introduction | |
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| Design Flow | |
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| Syntax | |
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| Title | |
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| Settings of Various Global Parameters | |
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| Listing of Sources and Active and Passive Elements | |
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| Analysis Statements | |
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| Complete SPICE Examples | |
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| Bipolar Transistors and Circuits | |
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| The Bipolar Junction Transistor | |
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| The Schottky-Barrier Diode | |
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| BJT Model for Circuit Simulation | |
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| Bipolar Transistor Inverter | |
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| Voltage Transfer Characteristics | |
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| Schottky-Clamped Inverter | |
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| BJT Inverter Switching Times | |
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| Bipolar Digital Gate Circuits | |
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| Voltage Transfer Characteristics | |
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| Propagation Delay Time | |
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| Input Clamp Diodes | |
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| Index | |