Boundary-Scan Handbook

Name: Boundary-Scan Handbook
Availability: InStock
ISBN: 9781402074967

ISBN-10: 1402074964

ISBN-13: 9781402074967

Edition: 3rd 2003 (Revised)

Authors: Kenneth P. Parker

List price: $249.00

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Description:

Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-1990, is a collection of design rules applied principally at the Integrated Circuit (IC) level that allow software to alleviate the growing cost of designing, producing and testing digital systems. A fundamental benefit of the standard is its ability to transform extremely difficult printed circuit board testing problems that could only be attacked with Ad-Hoc testing methods into well-structured problems that software can easily and swiftly solve. IEEE testing standards of the 1149 family are living entities that grow and change quickly. The Boundary-Scan Handbook, Third Edition is intended to describe these standards in simple…

Book details

List price: $249.00
Edition: 3rd
Copyright year: 2003
Publisher: Springer
Publication date: 6/30/2003
Binding: Hardcover
Pages: 373
Size: 6.25" wide x 9.25" long x 1.00" tall
Weight: 1.782
Language: English



List of Figures


List of Tables


List of Design-for-Test Rules


Preface to the First Edition


Preface to the Second Edition


Preface to the Third Edition


Acknowledgement



Boundary-Scan Basics and Vocabulary



Digital Test Before Boundary-Scan



Edge-Connector Functional Testing



In-Circuit Testing



The Philosophy of 1149.1



Basic Architecture



The TAP Controller



The Instruction Register



Data Registers



The Boundary Register



Optimizing a Boundary Register Cell Design



Architecture Summary



Field-Programmable IC Devices



Boundary-Scan Chains



Non-Invasive Operational Modes



Bypass



Idcode



Usercode



Sample



Preload



Pin-Permission Operational Modes



Extest



Intest



Runbist



Highz



Clamp



Exceptions Due to Clocking



Extensibility



Subordination of IEEE 1149.1



Costs and Benefits



Costs



Benefits



Trends



Other Testability Standards



Boundary-Scan Description Language (BSDL)



The Scope of BSDL



Testing



Compliance Assurance



Synthesis



Structure of BSDL



Entity Descriptions



Generic Parameter



Logical Port Description



Standard USE Statement



Use Statements



Component Conformance Statement



Device Package Pin Mappings



Grouped Port Identification



TAP Port Identification



Compliance Enable Description



Instruction Register Description



Optional Register Description



Register Access Description



Boundary-Scan Register Description



Runbist Execution Description



Intest Execution Description



User Extensions to BSDL



Design Warnings



Some advanced BSDL Topics



Merged Cells



Asymmetrical Drivers



BSDL Description of 74BCT8374



Packages and Package Bodies



STD_1149_1_2001



Cell Description Constants



Basic Cell Definitions BC_0 to BC_7



Cells BC_8 to BC_10 Introduced in 2001



User-Defined Boundary Cells



Definition of BSDL Extensions



Writing BSDL



Summary



Boundary-Scan Testing



Basic Boundary-Scan Testing



The 1149.1 Scanning Sequence



Basic Test Algorithm



The "Personal Tester" Versus ATE



In-Circuit Boundary-Scan



IC Test



IC BIST



Testing with Boundary-Scan Chains



1149.1 Chain Integrity



Interconnect Test



Connection Tests



Interaction Tests



BIST and Custom Tests



Porting Boundary-Scan Tests



Boundary-Scan Test Coverage



Summary



Advanced Boundary-Scan Topics



DC Parametric IC Tests



Sample Mode Tests



Concurrent Monitoring



Non-Scan IC Testing



Non-Digital Device Testing



Mixed Digital/Analog Testing



Multi-Chip Module Testing



Firmware Development Support



In-System Configuration



Flash Programming



Hardware Fault Insertion



Power Pin Testing



Design for Boundary-Scan Test



Integrated Circuit Level DFT



TAP Pin Placement



Power and Ground Distribution



Instruction Capture Pattern



Damage Resistant Drivers



Output Pins



Bidirectional Pins



Post-Lobotomy Behavior



IDCODEs



User-Defined Instructions



Creation and Verification of BSDL



Board-Level DFT



Chain Configurations



TCK/TMS Distribution



Mixed Logic Families



Board Level Conflicts



Control of Critical Nodes



Power Distribution



Boundary-Scan Masters



Post-Lobotomy Board Behavior



System-Level DFT



The MultiDrop Problem



Coordination with Other Standards



Summary



Analog Measurement Basics



Analog In-Circuit Testing



Analog Failures



Measuring an Impedance



Errors and Corrections



Measurement Hardware



Limited Access Testing



Node Voltage Analysis



Testing With Node Voltages



Limited Access Node Voltage Testing



The Mixed-Signal Test Environment



Summary



IEEE 1149.4: Analog Boundary-Scan



1149.4 Vocabulary and Basics



The Target Fault Spectrum



Extended Interconnect



Digital Pins



Analog Pins



General Architecture of an 1149.4 IC



Silicon "Switches"



The Analog Test Access Port (ATAP)



The Test Bus Interface Circuit (TBIC)



The Analog Boundary Module (ABM)



The Digital Boundary Module (DBM)



The 1149.4 Instruction Set



The EXTEST Instruction



The CLAMP Instruction



The HIGHZ Instruction



The PROBE Instruction



The RUNBIST Instruction



The INTEST Instruction



Other Provisions of 1149.4



Differential ATAP Port



Differential I/O



Partitioned Internal Test Buses



Specifications and Limits



Design for 1149.4 Testability



Integrated Circuit Level



Board Level



System Level



Summary



IEEE 1149.6: Testing Advanced I/O



The Advanced I/O Problem



Traditional Inter-IC Communication



Advanced Inter-IC Communication



AC Coupled Signal Paths



Testing Advanced I/O



1149.6 Vocabulary and Basics



Advanced I/O



Signal Pin Categories



Operational Modes



Test Facilities for AC Pins



Provisions for All Signal Pins



Provisions for AC Pin Drivers



AC/DC Selection Cells



Provisions for AC Pin Receivers



The Defect Model for 1149.6



The 1149.6 Test Receiver



Test Receiver Definitions



Transitions



Test Receiver DC Response



Test Receiver AC Response



Guaranteed AC-Coupling



An Integrated AC/DC Test Receiver



Initializing and Capturing Hysteretic Memory



BSDL Extensions for 1149.6



Boundary Registers Cells for 1149.6



STD_1149_6_2003



Example 1149.6 Device and BSDL



Design for 1149.6 Testability



Integrated Circuit Level DFT



Board-Level DFT



Summary



IEEE 1532: In-System Configuration



IEEE 1532 Vocabulary and Basics



Fixed System Pins



ISC System Pins



System Modal States



System I/O Behavior



ISC Pin I/O Cell Design



Programming Features of IEEE 1532



Core 1532 Programming Instructions



Programming a Single, Simple 1532 Device



Concurrent Programming of Multiple Devices



Design for IEEE 1532 Programmability



Epilog: What Next for 1149.1, 1149.4, 1149.6 and 1532?



BSDL Syntax Specifications



Conventions



Lexical elements of BSDL



Notes on syntax definition



BSDL Syntax



User Package Syntax



1149.6 Extention Attribute Syntax


Bibliography


Index