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Contributors | |
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Preface | |
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Introduction | |
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Introduction | |
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Sources of Power Consumption | |
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Low-Power versus Power-Aware Design | |
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Power Reduction Mechanisms in CMOS Circuits | |
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Power Reduction Techniques in Microelectronic Systems | |
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Book Organization and Overview | |
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Summary | |
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CMOS Device Technology Trends for Power-Constrained Applications | |
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Introduction | |
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CMOS Technology Summary | |
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Current CMOS Device Technology | |
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ITRS Projections | |
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Scaling Principles and Difficulties | |
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General Scaling | |
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Characteristic Scale Length | |
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Limits to Scaling | |
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Power-constained Scaling Limits | |
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Optimizing V[subscript DD] and V[subscript T] | |
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Optimizing Gate Insulator Thickness and Gate Length - the Optimal End to Scaling | |
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Discussion of the Optimizations | |
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Exploratory Technology | |
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Body- or Back-Gate Bias | |
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Strained Si | |
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Fully-Depleted SOI | |
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Double-gate FET Structures | |
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Low Temperature Operation for High Performance | |
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Summary | |
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Low Power Memory Design | |
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Introduction | |
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Flash Memories | |
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Flash Memory Cell Operation and Control Schemes | |
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Circuits Used in Flash Memories | |
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Ferroelectric Memory | |
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Basic Operation of FeRAM | |
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Low Voltage FeRAM Design | |
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Embedded DRAM | |
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Advantages of Embedded DRAM | |
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Low Voltage Embedded DRAM Design | |
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Summary | |
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Low-Power Digital Circuit Design | |
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Introduction | |
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Low Voltage Technologies | |
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Variable V[subscript DD] and V[subscript T] | |
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Dual V[subscript DD]'s | |
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Multiple V[subscript DD]'s and V[subscript T]'s | |
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Low Voltage SRAM | |
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Low Switching-Activity Techniques | |
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Low Capacitance Technologies | |
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Summary | |
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Low Voltage Analog Design | |
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Introduction | |
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Fundamental Limits to Low Power Consumption | |
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Practical Limitations for Achieving the Minimum Power Consumption | |
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Implications of Reduced Supply Voltage | |
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Speed-power-accuracy Trade-off in High Speed ADC's | |
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High-speed ADC Architecture | |
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Models for Matching in Deep-submicron Technologies | |
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Impact of Voltage Scaling on Trade-off in High-speed ADC's | |
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Slew Rate Dominated Circuits vs. Settling Time Dominated Circuits | |
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Solutions for Low Voltage ADC Design | |
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Technological Modifications | |
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System Level | |
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Architectural Level | |
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Comparison with Published ADC's | |
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Summary | |
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Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip | |
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Introduction | |
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Power Consumption in VLSI Chips | |
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Power Consumption of Clocking System in VLSI Chips | |
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High-Performance Flip-Flops | |
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Low-Power Flip-Flops | |
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Master-Slave Latch Pairs | |
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Statistical Power Reduction Flip-Flops | |
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Small-Swing Flip-Flops | |
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Double-Edge Triggered Flip-Flops | |
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Low-Swing Clock Double-Edge Triggered Flip-Flop | |
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Comparisons of Simulation Results | |
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More on Clocking Power-Saving Methodologies | |
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Clock Gating | |
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Embedded Logic in Flip-Flops | |
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Clock Buffer (Repeater) and Tree Design | |
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Potential Issues in Multi-GHz SoCs in VDSM Technology | |
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Comparison of Power-Saving Approaches | |
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Summary | |
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Power Optimization by Datapath Width Adjustment | |
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Introduction | |
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Power Consumption and Datapath Width | |
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Datapath Width and Area | |
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Energy Consumption and Datapath Width | |
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Dynamic Adjustment of Datapath Width | |
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Bit-Width Analysis | |
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Datapath Width Adjustment on a Soft-core Processor | |
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Case Studies | |
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ADPCM Decoder LSI | |
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MPEG-2 AAC Decoder | |
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MPEG-2 Video Decoder Processors | |
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Quality-Driven Design | |
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Summary | |
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Energy-Efficient Design of High-Speed Links | |
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Introduction | |
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Overview of Link Design | |
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Figures of Merit | |
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Transmitter | |
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Receiver | |
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Clock Synthesis and Timing Recovery | |
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Putting It Together | |
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Approaches for Energy Efficiency | |
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Parallelism | |
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Adaptive Power-Supply Regulation | |
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Putting It Together | |
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Examples | |
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Supply-Regulated PLL and DLL Design | |
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Adaptive-Supply Serial Links | |
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Low-Power Area-Efficient Hi-Speed I/O Circuit Techniques | |
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Putting It Together | |
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Summary | |
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System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing | |
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Introduction | |
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System-level Modeling and Design Exploration | |
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The SAN Modeling Paradigm | |
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The SAN Model Construction | |
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Performance Model Evaluation | |
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Case Study: Power-performance of the MPEG-2 Video Decoder Application | |
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System Specification | |
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Application Modeling | |
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Platform Modeling | |
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Mapping | |
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Results and Discussion | |
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Performance Results | |
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Power Results | |
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Microarchitecture-level Power Modeling | |
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Efficient Processor Design Exploration for Low Power | |
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Efficient Microarchitectural Power Simulation | |
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Design Exploration Trade-offs | |
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Implications of Application Profile on Energy-aware Computing | |
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On-the-fly Energy Optimal Configuration Detection and Optimization | |
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Energy Profiling in Hardware | |
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On-the-fly Optimization of the Processor Configuration | |
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Selective Dynamic Voltage Scaling | |
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Effectiveness of Microarchitecture Resource Scaling | |
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Comparison with Static Throttling Methods | |
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Summary | |
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Tools and Techniques for Integrated Hardware-Software Energy Optimizations | |
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Introduction | |
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Power Modeling | |
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Design of Simulators | |
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A SimOS-Based Energy Simulator | |
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Trimaran-based VLIW Energy Simulator | |
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Hardware-software Optimizations: Case Studies | |
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Studying the Impact of Kernel and Peripheral Energy Consumption | |
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Studying the Impact of Compiler Optimizations | |
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Studying the Impact of Architecture Optimizations | |
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Summary | |
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Power-Aware Communication Systems | |
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Introduction | |
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Where Does the Energy Go in Wireless Communications | |
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Electronic and RF Energy Consumption in Radios | |
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First-order Energy Model for Wireless Communication | |
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Power consumption in Short-range Radios | |
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Power Reduction and Management for Wireless Communications | |
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Lower Layer Techniques | |
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Dynamic Power Management of Radios | |
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More Lower-layer Energy-speed Control Knobs | |
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Energy-aware Medium Access Control | |
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Higher Layer Techniques | |
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Network Topology Management | |
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Energy-aware Data Routing | |
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Summary | |
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Power-Aware Wireless Microsensor Networks | |
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Introduction | |
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Node Energy Consumption Characteristics | |
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Hardware Architecture | |
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Digital Processing Energy | |
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Radio Transceiver Energy | |
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Power Awareness Through Energy Scalability | |
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Dynamic Voltage Scaling | |
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Ensembles of Systems | |
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Variable Radio Modulation | |
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Adaptive Forward Error Correction | |
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Power-aware Communication | |
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Low-Power Media Access Control Protocol | |
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Minimum Energy Multihop Forwarding | |
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Clustering and Aggregation | |
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Distributed Processing through System Partitioning | |
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Node Prototyping | |
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Hardware Architecture | |
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Measured Energy Consumption | |
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Future Directions | |
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Summary | |
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Circuit and System Level Power Management | |
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Introduction | |
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System-level Power Management Techniques | |
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Greedy Policy | |
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Fixed Time-out Policy | |
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Predictive Shut-down Policy | |
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Predictive Wake-up Policy | |
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Stochastic Methods | |
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Component-level Power Management Techniques | |
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Dynamic Power Minimization | |
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Leakage Power Minimization | |
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Summary | |
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Tools and Methodologies for Power Sensitive Design | |
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Introduction | |
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The Design Automation View | |
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Power Consumption Components | |
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Different Types of Power Tools | |
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Power Tool Data Requirements | |
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Different Types of Power Measurements | |
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Transistor Level Tools | |
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Transistor Level Analysis Tools | |
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Transistor Level Optimization Tools | |
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Transistor Level Characterization and Modeling Tools | |
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Derivative Transistor Level Tools | |
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Gate-level Tools | |
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Gate-Level Analysis Tools | |
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Gate-Level Optimization Tools | |
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Gate-Level Modeling Tools | |
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Derivative Gate-Level Tools | |
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Register Transfer-level Tools | |
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RTL Analysis Tools | |
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RTL Optimization Tools | |
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Behavior-level Tools | |
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Behavior-Level Analysis Tools | |
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Behavior-Level Optimization Tools | |
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System-level tools | |
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A Power-sensitive Design Methodology | |
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Power-Sensitive Design | |
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Feedback vs. Feed Forward | |
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A View to The Future | |
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Summary | |
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Reconfigurable Processors--the Road to Flexible Power-aware Computing | |
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Introduction | |
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Platform-Based DEsign | |
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Opportunities for energy minimization | |
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Voltage as a Design Variable | |
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Eliminating Architectural Waste | |
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Programmable Architectures--an Overview | |
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Architecture Models | |
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Homogeneous and Heterogeneous Architectures | |
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Agile Computing Systems (Heterogeneous Compute Systems-on-a-chip) | |
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The Berkeley Pleiades Platform [10] | |
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Concept | |
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Architecture | |
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Communication Network | |
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Benchmark Example: The Maia Chip [10] | |
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Architectural Innovations Enable Circuit-level Optimizations | |
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Dynamic Voltage Scaling | |
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Reconfigurable Low-swing Interconnect Network | |
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Summary | |
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Energy-efficient System-level Design | |
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Introduction | |
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Systems on Chips and Their Design | |
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SOC Case Studies | |
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Emotion Engine | |
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MPEG4 Core | |
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Single-chip Voice Recorder | |
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Design of Memory Systems | |
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On-chip Memory Hierarchy | |
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Explorative Techniques | |
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Memory Partitioning | |
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Extending the Memory Hierarchy | |
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Bandwidth Optimization | |
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Design of Interconnect Networks | |
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Signal Transmission on Chip | |
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Network Architectures and Control Protocols | |
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Energy-efficient Design: Techniques and Examples | |
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Software | |
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System Software | |
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Application Software | |
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Summary | |
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Index | |