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Power Aware Design Methodologies

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ISBN-10: 1402071523

ISBN-13: 9781402071522

Edition: 2002

Authors: Massoud Pedram, Jan M. Rabaey

List price: $279.99
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Power Aware Design Methodologies is on power-awareness in design. The difference between low-power design and power-awareness in design is that whereas low-power design refers to minimizing power with or without a performance constraint, power-aware design refers to maximizing some other performance metric, subject to a power budget (even while reducing power dissipation). Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and…    
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Book details

List price: $279.99
Copyright year: 2002
Publisher: Springer
Publication date: 6/30/2002
Binding: Hardcover
Pages: 522
Size: 6.25" wide x 9.25" long x 1.25" tall
Weight: 2.200
Language: English

Sources of Power Consumption
Low-Power versus Power-Aware Design
Power Reduction Mechanisms in CMOS Circuits
Power Reduction Techniques in Microelectronic Systems
Book Organization and Overview
CMOS Device Technology Trends for Power-Constrained Applications
CMOS Technology Summary
Current CMOS Device Technology
ITRS Projections
Scaling Principles and Difficulties
General Scaling
Characteristic Scale Length
Limits to Scaling
Power-constained Scaling Limits
Optimizing V[subscript DD] and V[subscript T]
Optimizing Gate Insulator Thickness and Gate Length - the Optimal End to Scaling
Discussion of the Optimizations
Exploratory Technology
Body- or Back-Gate Bias
Strained Si
Fully-Depleted SOI
Double-gate FET Structures
Low Temperature Operation for High Performance
Low Power Memory Design
Flash Memories
Flash Memory Cell Operation and Control Schemes
Circuits Used in Flash Memories
Ferroelectric Memory
Basic Operation of FeRAM
Low Voltage FeRAM Design
Embedded DRAM
Advantages of Embedded DRAM
Low Voltage Embedded DRAM Design
Low-Power Digital Circuit Design
Low Voltage Technologies
Variable V[subscript DD] and V[subscript T]
Dual V[subscript DD]'s
Multiple V[subscript DD]'s and V[subscript T]'s
Low Voltage SRAM
Low Switching-Activity Techniques
Low Capacitance Technologies
Low Voltage Analog Design
Fundamental Limits to Low Power Consumption
Practical Limitations for Achieving the Minimum Power Consumption
Implications of Reduced Supply Voltage
Speed-power-accuracy Trade-off in High Speed ADC's
High-speed ADC Architecture
Models for Matching in Deep-submicron Technologies
Impact of Voltage Scaling on Trade-off in High-speed ADC's
Slew Rate Dominated Circuits vs. Settling Time Dominated Circuits
Solutions for Low Voltage ADC Design
Technological Modifications
System Level
Architectural Level
Comparison with Published ADC's
Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
Power Consumption in VLSI Chips
Power Consumption of Clocking System in VLSI Chips
High-Performance Flip-Flops
Low-Power Flip-Flops
Master-Slave Latch Pairs
Statistical Power Reduction Flip-Flops
Small-Swing Flip-Flops
Double-Edge Triggered Flip-Flops
Low-Swing Clock Double-Edge Triggered Flip-Flop
Comparisons of Simulation Results
More on Clocking Power-Saving Methodologies
Clock Gating
Embedded Logic in Flip-Flops
Clock Buffer (Repeater) and Tree Design
Potential Issues in Multi-GHz SoCs in VDSM Technology
Comparison of Power-Saving Approaches
Power Optimization by Datapath Width Adjustment
Power Consumption and Datapath Width
Datapath Width and Area
Energy Consumption and Datapath Width
Dynamic Adjustment of Datapath Width
Bit-Width Analysis
Datapath Width Adjustment on a Soft-core Processor
Case Studies
MPEG-2 AAC Decoder
MPEG-2 Video Decoder Processors
Quality-Driven Design
Energy-Efficient Design of High-Speed Links
Overview of Link Design
Figures of Merit
Clock Synthesis and Timing Recovery
Putting It Together
Approaches for Energy Efficiency
Adaptive Power-Supply Regulation
Putting It Together
Supply-Regulated PLL and DLL Design
Adaptive-Supply Serial Links
Low-Power Area-Efficient Hi-Speed I/O Circuit Techniques
Putting It Together
System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing
System-level Modeling and Design Exploration
The SAN Modeling Paradigm
The SAN Model Construction
Performance Model Evaluation
Case Study: Power-performance of the MPEG-2 Video Decoder Application
System Specification
Application Modeling
Platform Modeling
Results and Discussion
Performance Results
Power Results
Microarchitecture-level Power Modeling
Efficient Processor Design Exploration for Low Power
Efficient Microarchitectural Power Simulation
Design Exploration Trade-offs
Implications of Application Profile on Energy-aware Computing
On-the-fly Energy Optimal Configuration Detection and Optimization
Energy Profiling in Hardware
On-the-fly Optimization of the Processor Configuration
Selective Dynamic Voltage Scaling
Effectiveness of Microarchitecture Resource Scaling
Comparison with Static Throttling Methods
Tools and Techniques for Integrated Hardware-Software Energy Optimizations
Power Modeling
Design of Simulators
A SimOS-Based Energy Simulator
Trimaran-based VLIW Energy Simulator
Hardware-software Optimizations: Case Studies
Studying the Impact of Kernel and Peripheral Energy Consumption
Studying the Impact of Compiler Optimizations
Studying the Impact of Architecture Optimizations
Power-Aware Communication Systems
Where Does the Energy Go in Wireless Communications
Electronic and RF Energy Consumption in Radios
First-order Energy Model for Wireless Communication
Power consumption in Short-range Radios
Power Reduction and Management for Wireless Communications
Lower Layer Techniques
Dynamic Power Management of Radios
More Lower-layer Energy-speed Control Knobs
Energy-aware Medium Access Control
Higher Layer Techniques
Network Topology Management
Energy-aware Data Routing
Power-Aware Wireless Microsensor Networks
Node Energy Consumption Characteristics
Hardware Architecture
Digital Processing Energy
Radio Transceiver Energy
Power Awareness Through Energy Scalability
Dynamic Voltage Scaling
Ensembles of Systems
Variable Radio Modulation
Adaptive Forward Error Correction
Power-aware Communication
Low-Power Media Access Control Protocol
Minimum Energy Multihop Forwarding
Clustering and Aggregation
Distributed Processing through System Partitioning
Node Prototyping
Hardware Architecture
Measured Energy Consumption
Future Directions
Circuit and System Level Power Management
System-level Power Management Techniques
Greedy Policy
Fixed Time-out Policy
Predictive Shut-down Policy
Predictive Wake-up Policy
Stochastic Methods
Component-level Power Management Techniques
Dynamic Power Minimization
Leakage Power Minimization
Tools and Methodologies for Power Sensitive Design
The Design Automation View
Power Consumption Components
Different Types of Power Tools
Power Tool Data Requirements
Different Types of Power Measurements
Transistor Level Tools
Transistor Level Analysis Tools
Transistor Level Optimization Tools
Transistor Level Characterization and Modeling Tools
Derivative Transistor Level Tools
Gate-level Tools
Gate-Level Analysis Tools
Gate-Level Optimization Tools
Gate-Level Modeling Tools
Derivative Gate-Level Tools
Register Transfer-level Tools
RTL Analysis Tools
RTL Optimization Tools
Behavior-level Tools
Behavior-Level Analysis Tools
Behavior-Level Optimization Tools
System-level tools
A Power-sensitive Design Methodology
Power-Sensitive Design
Feedback vs. Feed Forward
A View to The Future
Reconfigurable Processors--the Road to Flexible Power-aware Computing
Platform-Based DEsign
Opportunities for energy minimization
Voltage as a Design Variable
Eliminating Architectural Waste
Programmable Architectures--an Overview
Architecture Models
Homogeneous and Heterogeneous Architectures
Agile Computing Systems (Heterogeneous Compute Systems-on-a-chip)
The Berkeley Pleiades Platform [10]
Communication Network
Benchmark Example: The Maia Chip [10]
Architectural Innovations Enable Circuit-level Optimizations
Dynamic Voltage Scaling
Reconfigurable Low-swing Interconnect Network
Energy-efficient System-level Design
Systems on Chips and Their Design
SOC Case Studies
Emotion Engine
MPEG4 Core
Single-chip Voice Recorder
Design of Memory Systems
On-chip Memory Hierarchy
Explorative Techniques
Memory Partitioning
Extending the Memory Hierarchy
Bandwidth Optimization
Design of Interconnect Networks
Signal Transmission on Chip
Network Architectures and Control Protocols
Energy-efficient Design: Techniques and Examples
System Software
Application Software