Digital Systems Design Using VHDL

ISBN-10: 0534384625

ISBN-13: 9780534384623

Edition: 2nd 2008

Authors: Lizy Kurian John, Charles H. Roth, Charles H. Roth

List price: $201.95 Buy it from $16.29 Rent it from $79.80
30 day, 100% satisfaction guarantee

If an item you ordered from TextbookRush does not meet your expectations due to an error on our part, simply fill out a return request and then return it by mail within 30 days of ordering it for a full refund of item cost.

Learn more about our returns policy

Description:

Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design, the author introduces the basics of VHDL, and then incorporates more coverage of advanced VHDL topics. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process.
Used Starting from $27.71
Rent Starting from $79.80
what's this?
Rush Rewards U
Members Receive:
coins
coins
You have reached 400 XP and carrot coins. That is the daily max!
Study Briefs

Limited time offer: Get the first one free! (?)

All the information you need in one place! Each Study Brief is a summary of one specific subject; facts, figures, and explanations to help you learn faster.

Add to cart
Study Briefs
SQL Online content $4.95 $1.99
Add to cart
Study Briefs
MS Excel® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS Word® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS PowerPoint® 2010 Online content $4.95 $1.99
Customers also bought
Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading

Book details

List price: $201.95
Edition: 2nd
Copyright year: 2008
Publisher: Course Technology
Publication date: 3/30/2007
Binding: Hardcover
Pages: 592
Size: 8.50" wide x 9.75" long x 1.00" tall
Weight: 2.530
Language: English

Preface
Review Of Logic Design Fundamentals
Combinational Logic
Boolean Algebra and Algebraic Simplification
Karnaugh Maps
Designing with NAND and NOR Gates
Hazards in Combinational Networks
Flip-flops and Latches
Meanly Sequential Network Design
Design of a Moore Sequential Network
Equivalent States and Reduction of State Tables
Sequential Network Timing
Setup and Hold Times
Synchronous Design
Tristate Logic and Busses
Introduction To Vhdl Vhdl
Description of Combinational Networks
Modeling Flip-flops using VHDL Processes
VHDL Models for a Multiplexer
Compilation and Simulation of VHDL Code
Modeling a Sequential Machine
Variables, Signals, and Constants
Arrays
VHDL Operators
VHDL Functions
VHDL Procedures
Packages and Libraries
VHDL Model for a 74163 Counter
Designing With Programmable Logic Devices
Read-only Memories
Programmable Logic Arrays (PLAs)
Programmable Array Logic (PALs)
Other Sequential Programmable Logic Devices (PLDs)
Design of a Keypad Scanner
Design Of Networks For Arithmetic Operations
Design of a Serial Adder with Accumulator
State Graphs for Control Networks
Design of a Binary Multiplier
Multiplication of Signed Binary Numbers
Design of a Binary Divider
Digital Design With Sm Charts
State Machine Charts
Derivation of SM Charts
Realization of SM Charts
Implementation of the Dice Game
Alternative Realizations for SM Charts Using Microprogramming
Linked State Machines
Designing with programmable gate arrays and complex programmable logic devices XILINX 3000 Series FPGAs
Designing with FPGAs
XILINX 4000 Series FPGAs
Using a One-Hot State Assignment
Altera Complex Programmable Logic Devices (CPLDs)
Altera FLEX 10K Series CPLDs
Floating-Point Arithmetic
Representation of Floating-Point Numbers
Floating-Point Multiplication
Other Floating-Point Operations
Additional Topics In VHDL Attributes
Transport and Inertial Delays
Operator Overloading
Multivalued Logic and Signal Resolution
IEEE-1164 Standard Logic
Generics
Generate Statements
Synthesis of VHDL Code
Synthesis Examples
Files and TEXTIO
VHDL Models For Memories And Busses
Static RAM Memory
A Simplified 486 Bus Model
Interfacing Memory to a Microprocessor Bus
Hardware Testing And Design For Testability
Testing Combinational Logic
Testing Sequential Logic
Scan Testing
Boundary Scan
Built-In Self-Test
Design Examples Uart
Design
Description of the MC68HC05 Microcontroller
Design of Microcontroller CPU
Completion of the Microcontroller Design
Vhdl Language Summary
Bit Package
Textio Package
Behavioral Vhdl Code For M6805 CPU
M6805 CPU Vhdl Code For Synthesis
Projects
References
Index
Free shipping on orders over $35*

*A minimum purchase of $35 is required. Shipping is provided via FedEx SmartPost® and FedEx Express Saver®. Average delivery time is 1 – 5 business days, but is not guaranteed in that timeframe. Also allow 1 - 2 days for processing. Free shipping is eligible only in the continental United States and excludes Hawaii, Alaska and Puerto Rico. FedEx service marks used by permission."Marketplace" orders are not eligible for free or discounted shipping.

Learn more about the TextbookRush Marketplace.

×