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| Preface | |
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| Introduction | |
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| A Brief History of Computing | |
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| The Von Neumann Model | |
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| The System Bus Model | |
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| Levels of Machines | |
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| Upward Compatibility | |
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| The Levels | |
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| A Typical Computer System | |
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| Role of the Network | |
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| Organization of the Book | |
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| Case Study: What Happened to Supercomputers? | |
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| Data Representation | |
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| Fixed-Point Numbers | |
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| Range and Precision in Fixed-Point Numbers | |
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| The Associative Law of Algebra Does Not Always Hold in Computers | |
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| Radix Number Systems | |
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| Conversions Among Radices | |
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| An Early Look at Computer Arithmetic | |
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| Signed Fixed-Point Numbers | |
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| Floating-Point Numbers | |
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| Range and Precision in Floating-Point Numbers | |
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| Normalization and the Hidden Bit | |
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| Representing Floating-Point Numbers in the Computer-Preliminaries | |
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| Error in Floating-Point Representations | |
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| The IEEE 754 Floating-Point Standard | |
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| Case Study: Patriot Missile Defense Failure Caused by Loss of Precision | |
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| Character Codes | |
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| The ASCII Character Set | |
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| The EBCDIC Character Set | |
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| The Unicode Character Set | |
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| Arithmetic | |
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| Fixed-Point Addition and Subtraction | |
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| Two's Complement Addition and Subtraction | |
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| Sign Extension | |
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| Hardware Implementation of Adders and Subtractors | |
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| One's Complement Addition and Subtraction | |
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| Fixed-Point Multiplication and Division | |
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| Unsigned Multiplication | |
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| Unsigned Division | |
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| Signed Multiplication and Division | |
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| Floating-Point Arithmetic | |
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| Floating-Point Addition and Subtraction | |
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| Floating-Point Multiplication and Division | |
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| High-Performance Arithmetic | |
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| High-Performance Addition | |
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| High-Performance Multiplication | |
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| High-Performance Division | |
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| Residue Arithmetic | |
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| The Instruction Set Architecture | |
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| Hardware Components of the Instruction Set Architecture | |
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| The System Bus Model Revisited | |
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| Memory | |
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| The CPU | |
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| ARC, A RISC Computer | |
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| ARC Memory | |
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| ARC Registers | |
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| ARC Assembly Language Format | |
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| The ARC Instruction Set | |
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| ARC Instruction Formats | |
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| SPARC and ARC Data Formats | |
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| ARC Instruction Descriptions | |
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| Pseudo-Operations | |
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| Synthetic Instructions | |
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| Examples of Assembly Language Programs | |
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| Variations in Machine Architectures and Addressing | |
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| Performance of Instruction Set Architectures | |
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| Accessing Data in Memory-Addressing Modes | |
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| Subroutine Linkage and Stacks | |
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| Input and Output in Assembly Language | |
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| Case Study: The Java Virtual Machine ISA | |
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| Datapath and Control | |
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| Basics of the Microarchitecture | |
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| The Datapath | |
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| Datapath Overview | |
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| The Control Section-Microprogrammed | |
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| Timing | |
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| Developing the Microprogram | |
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| Traps and Interrupts | |
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| Nanoprogramming | |
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| The Control Section-Hardwired | |
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| Case Study: The VHDL Hardware Description Language | |
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| Background | |
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| What is VHDL? | |
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| A VHDL Specification of the Majority Function | |
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| Nine-Value Logic System | |
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| Case Study: What Happens When a Computer Boots Up? | |
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| Languages and the Machine | |
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| The Compilation Process | |
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| Steps in Compilation | |
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| The Compiler Mapping Specification | |
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| How the Compiler Maps the Three Instruction Classes into Assembly Code | |
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| Data Movement | |
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| Arithmetic Instructions | |
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| Program Control Flow | |
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| The Assembly Process | |
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| Assembly and Two-Pass Assemblers | |
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| Assembly and the Symbol Table | |
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| Final Tasks of the Assembler | |
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| Programs for Embedded vs. Virtual Memory Systems | |
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| Linking and Loading | |
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| Linking | |
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| Resolving External References | |
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| Loading | |
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| Macros | |
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| Quantitative Analyses of Program Execution | |
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| Quantitative Performance Analysis | |
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| From CISC to RISC | |
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| Pipelining the Datapath | |
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| Arithmetic, Branch, and Load-Store Instructions | |
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| Pipelining Instructions | |
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| Keeping the Pipeline Filled | |
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| Overlapping Register Windows | |
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| Low-Power Coding | |
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| Memory | |
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| The Memory Hierarchy | |
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| Random-Access Memory | |
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| Memory Chip Organization | |
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| Constructing Large RAMs From Small RAMs | |
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| Commercial Memory Modules | |
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| Read-Only Memory | |
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| Flash Memory | |
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| Case Study: Rambus Memory | |
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| Cache Memory | |
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| Associative Mapped Cache | |
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| Direct-Mapped Cache | |
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| Set-Associative Mapped Cache | |
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| Cache Performance | |
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| Hit Ratios and Effective Access Times | |
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| Multilevel Caches | |
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| Cache Management | |
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| Cache Coherency | |
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| Virtual Memory | |
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| Overlays | |
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| Paging | |
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| Segmentation | |
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| Protection | |
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| Fragmentation | |
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| The Translation Lookaside Buffer | |
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| Putting It All Together | |
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| Advanced Topics | |
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| Content-Addressable (Associative) Memories | |
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| Case Study: Associative Memory in Routers | |
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| Case Study: The Intel Pentium 4 Memory System | |
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| Buses and Peripherals | |
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| Parallel Bus Architectures | |
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| Bus Structure, Protocol, and Control | |
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| Bus Clocking | |
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| The Synchronous Bus | |
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| The Asynchronous Bus | |
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| Bus Arbitration-Masters and Slaves | |
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| Bridge-Based Bus Architectures | |
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| Internal Communication Methodologies | |
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| Programmed I/O | |
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| Interrupt-Driven I/O | |
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| Direct Memory Access (DMA) | |
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| Case Study: Communication on the Intel Pentium Architecture | |
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| System Clock, Bus Clock, and Bus Speeds | |
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| Address, Data, Memory, and I/O Capabilities | |
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| Data Words Have Soft Alignment | |
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| Bus Cycles in the Pentium family | |
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| Memory Read and Write Bus Cycles | |
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| The Burst Read Bus Cycle | |
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| Bus Hold for Request by Bus Master | |
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| Data Transfer Rates | |
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| Serial Bus Architectures | |
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| RS-232 | |
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| Universal Serial Bus (USB) | |
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| Firewire | |
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| Mass Storage | |
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| Magnetic Disks | |
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| Magnetic Tape | |
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| Optical Disks | |
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| RAID-Redundant Arrays of Inexpensive Disks | |
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| Input Devices | |
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| Keyboards | |
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| Tablets | |
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| Mice and Trackballs | |
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| Touch-Sensitive Pen-Based Display | |
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| Joysticks | |
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| Output Devices | |
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| Laser Printers | |
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| Video Displays | |
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| Liquid Crystal Displays (LCDs) | |
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| Case Study: Graphics Processing Unit | |
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| Case Study: How a Virus Infects a Machine | |
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| Networking and Communication | |
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| A Few Modulation Schemes | |
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| Transmission Media | |
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| Two-Wire Open Lines | |
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| Twisted-Pair Lines | |
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| Coaxial Cable | |
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| Optical Fiber | |
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| Satellites | |
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| Terrestrial Microwave | |
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| Radio | |
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| Error Detection and Correction | |
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| Bit Error Rate Defined | |
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| Hamming Codes | |
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| Vertical Redundancy Checking | |
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| Cyclic Redundancy Checking | |
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| Networking and Network Device Architectures | |
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| The OSI Model | |
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| Topologies | |
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| Ethernet | |
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| Hubs, Bridges, Switches, Routers, and Gateways | |
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| Storage Area Networks | |
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| Case Study: Cisco Router Architecture | |
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| Advanced Computer Architecture | |
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| Parallel Architecture | |
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| Measuring Performance | |
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| The Flynn Taxonomy | |
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| Interconnection Networks | |
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| Mapping an Algorithm Onto a Parallel Architecture | |
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| Superscalar Machines and the PowerPC | |
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| Instruction Set Architecture of the PowerPC | |
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| Hardware Architecture of the PowerPC | |
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| VLIW Machines, and the Itanium | |
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| Case Study: The Intel IA-64 (Itanium) Architecture | |
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| Background-the 80x86 CISC Architecture | |
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| The Itanium: an Epic Architecture | |
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| Case Study: Extensions to the Instruction Set-The Intel MMX/SSEX and Motorola AltiVec SIMD Instructions | |
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| Background | |
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| The Base Architectures | |
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| VECTOR Registers | |
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| Vector Arithmetic Operations | |
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| Vector Compare Operations | |
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| Case Study Summary | |
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| Programmable Logic Devices and Custom ICs | |
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| The Role of CAD Tools in PLD Design | |
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| PLAS and PALS | |
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| Complex Programmable Logic Devices | |
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| Field-Programmable Gate Arrays | |
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| Application-Specific Integrated Circuits | |
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| Unconventional Architectures | |
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| DNA Computing | |
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| Quantum Computing | |
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| Multi-valued Logic | |
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| Neural Networks | |
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| Digital Logic | |
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| Introduction | |
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| Combinational Logic | |
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| Truth Tables | |
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| Logic Gates | |
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| Electronic Implementation of Logic Gates | |
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| Tri-State Buffers | |
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| Properties of Boolean Algebra | |
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| The Sum-of-Products Form and Logic Diagrams | |
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| The Product-of-Sums Form | |
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| Positive vs. Negative Logic | |
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| The Data Sheet | |
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| Digital Components | |
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| Levels of Integration | |
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| Multiplexers | |
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| Demultiplexers | |
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| Decoders | |
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| Priority Encoders | |
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| Programmable Logic Arrays | |
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| Sequential Logic | |
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| The S-R Flip-Flop | |
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| The Clocked S-R Flip-Flop | |
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| The D Flip-Flop and the Master-Slave Configuration | |
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| J-K and T Flip-Flops | |
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| Design of Finite State Machines | |
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| Mealy vs. Moore Machines | |
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| Registers | |
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| Counters | |
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| Reduction of Combinational Logic and Sequential Logic | |
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| Reduction of Two-Level Expressions | |
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| The Algebraic Method | |
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| The K-Map Method | |
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| The Tabular Method | |
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| Logic Reduction: Effect on Speed and Performance | |
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| State Reduction | |
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| Using ARCTools | |
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| Introduction | |
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| Accessing and Launching ARCTools | |
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| Launching ARCTools | |
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| The ARC Assembler | |
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| Loading, Assembling, and Examining a File | |
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| Saving Files | |
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| Loading Files into the Simulator | |
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| The ARC Simulator | |
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| Instructions and Pseudo Instructions Recognized by ARCTools | |
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| Instructions-Actual, Synthetic, and Pseudo | |
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| The Macroprocessor | |
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| Measuring Program Performance | |
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| The TimeModel configuration Editor | |
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| Memory/IO Parameters | |
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| TimeModel's Statistics Window | |
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| The Cache Simulator View | |
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| Index | |