High-Speed Digital System Design A Handbook of Interconnect Theory and Design Practices

ISBN-10: 0471360902

ISBN-13: 9780471360902

Edition: 2000

List price: $156.00
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Dealing with the design of interconnections between integral parts of a computer, this title covers a field which is rapidly changing due to the ever increasing operating speeds of microprocessors, causing circuits to behave in unusual ways.
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Book details

List price: $156.00
Copyright year: 2000
Publisher: John Wiley & Sons, Incorporated
Publication date: 9/8/2000
Binding: Hardcover
Pages: 362
Size: 6.25" wide x 9.25" long x 1.00" tall
Weight: 1.386
Language: English

STEPHEN H. HALL is a Senior Staff Engineer at Intel Corporation, where he leads a team focused on the research of new modeling and measurement solutions for channel speeds as high as 30Gb/sec. Previously at Intel, he was the lead designer for desktop and server buses on Pentiumr II, III, and IV based systems, coordinated research in the area of high-speed signaling with multiple universities, led research and development teams in the area of high-speed modeling, and taught signal integrity courses to engineers in two countries. He is also the author of High-Speed Digital System Design (Wiley).HOWARD L. HECK is a Principal Engineer at Intel Corporation, where he leads development of the signaling specifications and solutions for USB 3.0. He also teaches high-speed digital interconnect design at the Oregon Graduate Institute, is a Senior Member of the IEEE, and holds five patents in the area of high-performance packaging and interconnects, with five more pending.

The Importance of Interconnect Design
The Basics
The Past and the Future
Ideal Transmission Line Fundamentals
Transmission Line Structures on a PCB or MCM
Wave Propagation
Transmission Line Parameters
Characteristic Impedance
Propagation Velocity, Time, and Distance
Equivalent Circuit Models for SPICE Simulation
Launching Initial Wave and Transmission Line Reflections
Initial Wave
Multiple Reflections
Effect of Rise Time on Reflections
Reflections From Reactive Loads
Termination Schemes to Eliminate Reflections
Additional Examples
Calculating the Cross-Sectional Geometry of the PCB
Calculating the Propagation Delay
Determining the Wave Shape Seen at the Receiver
Creating an Equivalent Circuit
Mutual Inductance and Mutual Capacitance
Inductance and Capacitance Matrix
Field Simulators
Crosstalk-Induced Noise
Simulating Crosstalk Using Equivalent Circuit Models
Crosstalk-Induced Flight Time and Signal Integrity Variations
Effect of Switching Patterns on Transmission Line Performance
Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model
Crosstalk Trends
Termination of Odd- and Even-Mode Transmission Line Pairs
Pi Termination Network
T Termination Network
Minimization of Crosstalk
Additional Examples
Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing
Determining if Crosstalk Will Induce False Triggers
Nonideal Interconnect Issues
Transmission Line Losses
Conductor DC Losses
Dielectric DC Losses
Skin Effect
Frequency-Dependent Dielectric Losses
Variations in the Dielectric Constant
Serpentine Traces
Intersymbol Interference
Effects of 90[deg] Bends
Effect of Topology
Connectors, Packages, and Vias
Series Inductance
Shunt Capacitance
Connector Crosstalk
Effects of Inductively Coupled Connector Pin Fields
Connector Design Guidelines
Chip Packages
Common Types of Packages
Creating a Package Model
Effects of a Package
Optimal Pin-Outs
Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery
Nonideal Current Return Paths
Path of Least Inductance
Signals Traversing a Ground Gap
Signals That Change Reference Planes
Signals Referenced to a Power or a Ground Plane
Other Nonideal Return Path Scenarios
Differential Signals
Local Power Delivery Networks
Determining the Local Decoupling Requirements for High-Speed I/O
System-Level Power Delivery
Choosing a Decoupling Capacitor
Frequency Response of a Power Delivery System
Minimizing SSN
Buffer Modeling
Types of Models
Basic CMOS Output Buffer
Basic Operation
Linear Modeling of the CMOS Buffer
Behavioral Modeling of the Basic CMOS Buffer
Output Buffers That Operate in the Saturation Region
Digital Timing Analysis
Common-Clock Timing
Common-Clock Timing Equations
Source Synchronous Timing
Source Synchronous Timing Equations
Deriving Source Synchronous Timing Equations from an Eye Diagram
Alternative Source Synchronous Schemes
Alternative Bus Signaling Techniques
Incident Clocking
Embedded Clock
Design Methodologies
Worst-Case Timing Spreadsheet
Statistical Spreadsheets
Timing Metrics, Signal Quality Metrics, and Test Loads
Voltage Reference Uncertainty
Simulation Reference Loads
Flight Time
Flight-Time Skew
Signal Integrity
Design Optimization
Paper Analysis
Routing Study
Sensitivity Analysis
Initial Trend and Significance Analysis
Ordered Parameter Sweeps
Phase 1 Solution Space
Phase 2 Solution Space
Phase 3 Solution Space
Design Guidelines
General Rules of Thumb to Follow When Designing a System
Radiated Emissions Compliance and System Noise Minimization
FCC Radiated Emission Specifications
Physical Mechanisms of Radiation
Differential-Mode Radiation
Common-Mode Radiation
Wave Impedance
Decoupling and Choking
High-Frequency Decoupling at the System Level
Choking Cables and Localized Power and Ground Planes
Low-Frequency Decoupling and Ground Isolation
Additional PCB Design Criteria, Package Considerations, and Pin-Outs
Placement of High-Speed Components and Traces
Pin Assignments and Package Choice
Enclosure (Chassis) Considerations
Shielding Basics
Spread Spectrum Clocking
High-Speed Measurement Techniques
Digital Oscilloscopes
Other Effects
Time-Domain Reflectometry
TDR Theory
Measurement Factors
TDR Accuracy
Launch Parasitics
Probe Types
Interface Transmission Loss
Cable Loss
Amplitude Offset Error
Impedance Measurement
Accurate Characterization of Impedance
Measurement Region in TDR Impedance Profile
Odd- and Even-Mode Impedance
Crosstalk Noise
Propagation Velocity
Length Difference Method
Y-Intercept Method
TDT Method
Vector Network Analyzer
Introduction to S Parameters
One-Port Measurements (Z[subscript o],L,C)
Two-Port Measurements (T[subscript d], Attenuation, Crosstalk)
Calibration for One-Port Measurements
Calibration for Two-Port Measurements
Calibration Verification
Alternative Characteristic Impedance Formulas
Symmetric Stripline
Offset Stripline
GTL Current-Mode Analysis
Basic GTL Operation
GTL Transitions When a Middle Agent Is Driving
GTL Transitions When an End Agent With a Termination Is Driving
Transitions When There is a Pull-Up at the Middle Agent
Frequency-Domain Components in a Digital Signal
Useful S-Parameter Conversions
ABCD, Z, and Y Parameters
Normalizing the S Matrix to a Different Characteristic Impedance
Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S[subscript 21] Measurements
Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Line
Definition of the Decibel
FCC Emission Limits
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