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Digital Design of Signal Processing Systems A Practical Approach

ISBN-10: 047074183X

ISBN-13: 9780470741832

Edition: 2010

Authors: Shoab Ahmed Khan

List price: $90.95
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Description:

Digital Design of Signal Processing Systems: A Practical Approach offers a practical guide to designing efficient digital systems, covering the complete spectrum of digital design from a DSP (digital signal processing) perspective. Focusing on digital design techniques of implementing DSP algorithms in hardware, this book is accompanied by many design examples to illustrate the methodology for clarity. Offers a good number of design examples to illustrate the methodology. Provides a comprehensive account of converting floating-point algorithm implementation to fixed-point algorithm. Progresses chapter by chapter to increasingly more advanced topics allowing the reader to grasp the basic principles and build upon these foundations. Written by an author with over 14 years of industrial experience. Companion website hosting code for design examples.
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Book details

List price: $90.95
Copyright year: 2010
Publisher: John Wiley & Sons, Limited
Publication date: 1/28/2011
Binding: Hardcover
Pages: 606
Size: 7.00" wide x 10.00" long x 1.50" tall
Weight: 2.530
Language: English

Preface
Acknowledgement
Introduction to Digital Design of Signal Processing Systems
Fueling the Innovation: Moore's Law
Digital Systems
Examples of Digital Systems
Example: The Backplane of a Router
Digital Design Process
Digital Design Competing Objectives
Synchronous Digital Hardware Systems
Design Strategies
References
Digital Design Using HDL
Introduction to Verilog
System Design Flow
Verilog HDL
Four Levels of Abstraction
Verification in HW Design
System Verilog
Exercise
References
System Design Flow and Fixed-Point Arithmetic
System Design Flow
Representations and Numbers
Floating-point Format
Qn.m Format for Fixed-point Arithmetic
Floating-Point to Fixed-Point Conversion
Block Floating-Point Format
Digital Filters Forms
Exercise
References
DSP System Representations and Mapping on Fully Dedicated Architecture
Introduction
Discrete Real-Time System
Synchronous Digital Hardware Systems
Kahn Process Network (KPN)
Representation Methods of DSP systems
Performance Measures
Fully Dedicated Architecture
Pipelining in Fully Dedicated Architecture
Selecting Basic Building Blocks
DFG to HW Synthesis
Exercise
References
Design Options for Basic Building Blocks
Introduction
Embedded Processors and Arithmetic Units in FPGAs
Instantiation of Embedded Blocks
Basic Building Blocks
Adders
Barrel Shifter
Parallel Multiplier Architectures
Cary Save Adder (CSA) and Compressors
Compression Trees
2's Complement Signed Multiplier
Compression Trees for Multi Operand Addition
Algorithm Transformations for CSA
Exercise
References
Multiplierless Multiplication by Constants
Introduction
Canonic Sign Digit (CSD) Representation
Minimum Signed Digit Representation
Multiplication by Constant in Signal Processing Algorithm
Fully Dedicated Architecture for Direct Form FIR Filter
Transposed Direct Form FIR Filter
Complexity Reduction
Distributed Arithmetic
FFT Architecture using FIR Filter Structure
Exercise
References
Pipelining, Retiming, Look-ahead Transformation and Polyphase Decomposition
Introduction
Pipelining and Retiming
Digital Design of Feedback Systems
C-slow Retiming
Look Ahead Transformation for IIR filters
Polyphase Structure for Decimation and Interpolation Applications
Exercise
References
Unfolding and Folding Architectures
Introduction
Sampling Rate Considerations
Unfolding Techniques
Folding Techniques
Folding Regular Structured DFGs
Mathematical Transformation for Folding
Exercise
References
Finite State Machine-based Design
Time Shared Architecture Design Examples
Sequencing and Control
Algorithm State Machine Representation
FSM Optimization for Low Power and Area
Design for Testability
Testing FSMs
Sequence Conformance
Coverage Metrics for Design Validation
Methods for Reducing Power of a State Machine
Exercise
References
Micro program State Machines
Introduction
Micro programmed Controller
Counter-based State Machine Implementation
A Loadable Counter-based Micro-Program FSM
Counter-based Micro-Program FSM with Conditional Branching
Register Based Controller
Micro-program State Machine with Subroutine Support
Micro-program State Machine with Nested Loop Support
Design Example of a Wavelet Processor
References
Micro-Programmed-based Adaptive Filtering Applications
Introduction
Adaptive Filters Configurations
Adaptive Algorithms
Channel Equalizer using NLMS
Echo Canceller
Micro-Coded State Machine based Design for Adaptive Algorithm
Architecture of LEC Micro-coded Accelerator
Exercise
References
Exploring Design Options for CORDIC based DDFS Architectures
Introduction
Direct Digital Frequency Synthesizer
Design of a Basic DDFS
CORDIC Algorithm
HW Mapping of Modified CORDIC Algorithm
Exercise
References
Digital Design of Communication Systems
Top-level Design Options
Digital Communication System
Source Encoding
Encryption
Channel Coding
Digital Baseband Modulation
Exercise
References