Advanced FPGA Design Architecture, Implementation, and Optimization

Name: Advanced FPGA Design Architecture, Implementation, and Optimization
Price: 114.71 USD
Availability: InStock
ISBN: 9780470054376

ISBN-10: 0470054379

ISBN-13: 9780470054376

Edition: 2007

Authors: Steve Kilts

List price: $148.95

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Description:

Advanced FPGA Design provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer needs to be mentored for approximately a year before these principles are understood and utilized. It covers essential topics for designing FPGAs beyond moderate complexity. It assists the reader in advancing to a higher level of capability when access to the appropriate mentorship is not available, or if learning the difficult way is not desirable.

Book details

List price: $148.95
Copyright year: 2007
Publisher: John Wiley & Sons, Incorporated
Publication date: 6/29/2007
Binding: Hardcover
Pages: 352
Size: 6.40" wide x 9.50" long x 0.89" tall
Weight: 1.562
Language: English



Preface


Acknowledgments



Architecting Speed



High Throughput



Low Latency



Timing



Add Register Layers



Parallel Structures



Flatten Logic Structures



Register Balancing



Reorder Paths



Summary of Key Points



Architecting Area



Rolling Up the Pipeline



Control-Based Logic Reuse



Resource Sharing



Impact of Reset on Area



Resources Without Reset



Resources Without Set



Resources Without Asynchronous Reset



Resetting RAM



Utilizing Set/Reset Flip-Flop Pins



Summary of Key Points



Architecting Power



Clock Control



Clock Skew



Managing Skew



Input Control



Reducing the Voltage Supply



Dual-Edge Triggered Flip-Flops



Modifying Terminations



Summary of Key Points



Example Design: The Advanced Encryption Standard



AES Architectures



One Stage for Sub-bytes



Zero Stages for Shift Rows



Two Pipeline Stages for Mix-Column



One Stage for Add Round Key



Compact Architecture



Partially Pipelined Architecture



Fully Pipelined Architecture



Performance Versus Area



Other Optimizations



High-Level Design



Abstract Design Techniques



Graphical State Machines



DSP Design



Software/Hardware Codesign



Summary of Key Points



Clock Domains



Crossing Clock Domains



Metastability



Solution 1: Phase Control



Solution 2: Double Flopping



Solution 3: FIFO Structure



Partitioning Synchronizer Blocks



Gated Clocks in ASIC Prototypes



Clocks Module



Gating Removal



Summary of Key Points



Example Design: I2S Versus SPDIF



I2S



Protocol



Hardware Architecture



Analysis



SPDIF



Protocol



Hardware Architecture



Analysis



Implementing Math Functions



Hardware Division



Multiply and Shift



Iterative Division



The Goldschmidt Method



Taylor and Maclaurin Series Expansion



The CORDIC Algorithm



Summary of Key Points



Example Design: Floating-Point Unit



Floating-Point Formats



Pipelined Architecture



Verilog Implementation



Resources and Performance



Reset Circuits



Asynchronous Versus Synchronous



Problems with Fully Asynchronous Resets



Fully Synchronized Resets



Asynchronous Assertion, Synchronous Deassertion



Mixing Reset Types



Nonresetable Flip-Flops



Internally Generated Resets



Multiple Clock Domains



Summary of Key Points



Advanced Simulation



Testbench Architecture



Testbench Components



Testbench Flow



Main Thread



Clocks and Resets



Test Cases



System Stimulus



MATLAB



Bus-Functional Models



Code Coverage



Gate-Level Simulations



Toggle Coverage



Run-Time Traps



Timescale



Glitch Rejection



Combinatorial Delay Modeling



Summary of Key Points



Coding for Synthesis



Decision Trees



Priority Versus Parallel



Full Conditions



Multiple Control Branches



Traps



Blocking Versus Nonblocking



For-Loops



Combinatorial Loops



Inferred Latches



Design Organization



Partitioning



Data Path Versus Control



Clock and Reset Structures



Multiple Instantiations



Parameterization



Definitions



Parameters



Parameters in Verilog-2001



Summary of Key Points



Example Design: The Secure Hash Algorithm



SHA-1 Architecture



Implementation Results



Synthesis Optimization



Speed Versus Area



Resource Sharing



Pipelining, Retiming, and Register Balancing



The Effect of Reset on Register Balancing



Resynchronization Registers



FSM Compilation



Removal of Unreachable States



Black Boxes



Physical Synthesis



Forward Annotation Versus Back-Annotation



Graph-Based Physical Synthesis



Summary of Key Points



Floorplanning



Design Partitioning



Critical-Path Floorplanning



Floorplanning Dangers



Optimal Floorplanning



Data Path



High Fan-Out



Device Structure



Reusability



Reducing Power Dissipation



Summary of Key Points



Place and Route Optimization



Optimal Constraints



Relationship between Placement and Routing



Logic Replication



Optimization across Hierarchy



I/O Registers



Pack Factor



Mapping Logic into RAM



Register Ordering



Placement Seed



Guided Place and Route



Summary of Key Points



Example Design: Microprocessor



SRC Architecture



Synthesis Optimizations



Speed Versus Area



Pipelining



Physical Synthesis



Floorplan Optimizations



Partitioned Floorplan



Critical-Path Floorplan: Abstraction 1



Critical-Path Floorplan: Abstraction 2



Static Timing Analysis



Standard Analysis



Latches



Asynchronous Circuits



Combinatorial Feedback



Summary of Key Points



PCB Issues



Power Supply



Supply Requirements



Regulation



Decoupling Capacitors



Concept



Calculating Values



Capacitor Placement



Summary of Key Points








Bibliography


Index