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| The Fabrics | |
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| Introduction | |
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| A Historical Perspective | |
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| Issues in Digital Integrated Circuit Design | |
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| Quality Metrics of a Digital Design | |
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| The Manufacturing Process | |
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| The CMOS Manufacturing Process | |
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| Design Rules-The Contract between Designer and Process Engineer | |
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| Packaging Integrated Circuits | |
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| Perspective-Trends in Process Technology | |
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| The Devices | |
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| The Diode | |
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| The MOS(FET) Transistor | |
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| A Word on Process Variations | |
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| Perspective: Technology Scaling | |
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| The Wire | |
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| A First Glance | |
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| Interconnect Parameters-Capitance, Resistance, and Inductance | |
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| Electrical Wire Models | |
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| SPICE Wire Models | |
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| Perspective: A Look into the Future | |
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| A Circuit Perspective | |
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| The CMOS Inverter | |
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| The Static CMOS Inverter-An Intuitive Perspective | |
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| Evaluating the Robustness of the CMOS Inverter: The Static Behavior | |
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| Performance of CMOS Inverter: The Dynamic Behavior | |
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| Power, Energy, and Energy-Delay | |
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| Perspective: Technology Scaling and Its Impact on the Inverter Metrics | |
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| Designing Combinational Logic Gates in CMOS | |
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| Static CMOS Design | |
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| Dynamic CMOS Design | |
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| How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era | |
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| Designing Sequential Logic Circuits | |
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| Timing Metrics for Sequential Circuits | |
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| Classification of Memory Elements | |
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| Static Latches and Registers | |
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| Dynamic Latches and Registers | |
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| Pulse Registers | |
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| Sense-Amplifier Based Registers | |
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| Pipelining: An Approach to Optimize Sequential Circuits | |
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| Non-Bistable Sequential Circuits | |
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| Perspective: Choosing a Clocking Strategy | |
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| A System Perspective | |
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| Implementation Strategies for Digital ICS | |
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| From Custom to Semicustom and Structured-Array Design Approaches | |
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| Custom Circuit Design | |
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| Cell-Based Design Methodology | |
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| Array-Based Implementation Approaches | |
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| Perspective-The Implementation Platform of the Future | |
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| Coping with Interconnect | |
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| Capacitive Parasitics | |
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| Resistive Parasitics | |
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| Inductive Parasitics | |
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| Advanced Interconnect Techniques | |
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| Perspective: Networks-on-a-Chip | |
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| Timing Issues in Digital Circuits | |
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| Timing Classification of Digital Systems | |
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| Synchronous Design-An In-Depth Perspective | |
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| Self-Timed Circuit Design | |
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| Synchronizers and Arbiters | |
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| Clock Synthesis and Synchronization Using a Phased-Locked Loop | |
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| Future Directions and Perspectives | |
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| Designing Arithmetic Building Blocks | |
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| Datapaths in Digital Processor Architectures | |
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| The Adder | |
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| The Multiplier | |
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| The Shifter | |
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| Other Arithmetic Operators | |
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| Power and Spped Trade-Offs in Datapath Structures | |
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| Perspective: Design as a Trade-off | |
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| Designing Memory and Array Structures | |
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| The Memory Core | |
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| Memory Peripheral Circuitry | |
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| Memory Reliability and Yield | |
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| Power Dissipation in Memories | |
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| Case Studies in Memory Design | |
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| Perspective: Semiconductor Memory Trends and Evolutions | |
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| Problem Solutions | |
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| Index | |