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Digital Integrated Circuits A Design Perspective

ISBN-10: 0131786091

ISBN-13: 9780131786097

Edition: 1996

Authors: Jan M. Rabaey

List price: $115.00
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Description:

Intended for use in an undergraduate senior-level digital circuit design class. Advanced material appropriate for graduate courses. Progressive in content and form, this practical text successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design. Beginning with solid discussions on the operation of electronic devices and and in-depth analysis of the nucleus of digital design, the text maintains a consistent, logical flow of subject matter throughout, addressing today's most significant and compelling industry topics: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
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Book details

List price: $115.00
Copyright year: 1996
Publisher: Prentice Hall PTR
Publication date: 12/29/1995
Binding: Hardcover
Pages: 702
Size: 7.50" wide x 10.00" long x 1.25" tall
Weight: 2.596
Language: English

The Fabrics
Introduction
A Historical Perspective
Issues in Digital Integrated Circuit Design
Quality Metrics of a Digital Design
The Manufacturing Process
The CMOS Manufacturing Process
Design Rules-The Contract between Designer and Process Engineer
Packaging Integrated Circuits
Perspective-Trends in Process Technology
The Devices
The Diode
The MOS(FET) Transistor
A Word on Process Variations
Perspective: Technology Scaling
The Wire
A First Glance
Interconnect Parameters-Capitance, Resistance, and Inductance
Electrical Wire Models
SPICE Wire Models
Perspective: A Look into the Future
A Circuit Perspective
The CMOS Inverter
The Static CMOS Inverter-An Intuitive Perspective
Evaluating the Robustness of the CMOS Inverter: The Static Behavior
Performance of CMOS Inverter: The Dynamic Behavior
Power, Energy, and Energy-Delay
Perspective: Technology Scaling and Its Impact on the Inverter Metrics
Designing Combinational Logic Gates in CMOS
Static CMOS Design
Dynamic CMOS Design
How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era
Designing Sequential Logic Circuits
Timing Metrics for Sequential Circuits
Classification of Memory Elements
Static Latches and Registers
Dynamic Latches and Registers
Pulse Registers
Sense-Amplifier Based Registers
Pipelining: An Approach to Optimize Sequential Circuits
Non-Bistable Sequential Circuits
Perspective: Choosing a Clocking Strategy
A System Perspective
Implementation Strategies for Digital ICS
From Custom to Semicustom and Structured-Array Design Approaches
Custom Circuit Design
Cell-Based Design Methodology
Array-Based Implementation Approaches
Perspective-The Implementation Platform of the Future
Coping with Interconnect
Capacitive Parasitics
Resistive Parasitics
Inductive Parasitics
Advanced Interconnect Techniques
Perspective: Networks-on-a-Chip
Timing Issues in Digital Circuits
Timing Classification of Digital Systems
Synchronous Design-An In-Depth Perspective
Self-Timed Circuit Design
Synchronizers and Arbiters
Clock Synthesis and Synchronization Using a Phased-Locked Loop
Future Directions and Perspectives
Designing Arithmetic Building Blocks
Datapaths in Digital Processor Architectures
The Adder
The Multiplier
The Shifter
Other Arithmetic Operators
Power and Spped Trade-Offs in Datapath Structures
Perspective: Design as a Trade-off
Designing Memory and Array Structures
The Memory Core
Memory Peripheral Circuitry
Memory Reliability and Yield
Power Dissipation in Memories
Case Studies in Memory Design
Perspective: Semiconductor Memory Trends and Evolutions
Problem Solutions
Index