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| Introductory Concepts | |
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| Numerical Representation | |
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| Digital and Analog Systems | |
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| Digital Number Systems | |
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| Representing Binary Quantities | |
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| Digital Circuits/Logic Circuits | |
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| Parallel and Serial Transmission | |
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| Memory | |
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| Digital Computers | |
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| Number Systems and Codes | |
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| Binary-to-Decimal Conversions | |
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| Decimal-to-Binary Conversions | |
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| Hexadecimal Number System | |
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| BCD Code | |
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| The Gray Code | |
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| Putting it All Together | |
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| The Byte, Nibble, and Word | |
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| Alphanumeric Codes | |
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| Parity Method for Error Detection | |
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| Applications | |
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| Describing Logic Circuits | |
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| Truth Tables | |
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| OR Operation with OR Gates | |
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| AND Operation with AND Gates | |
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| NOT Operation | |
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| Describing Logic Circuits Algebraically | |
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| Evaluating Logic-Circuit Outputs | |
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| Implementing Circuits from Boolean Expressions | |
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| NOR Gates and NAND Gates | |
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| Boolean Theorems | |
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| DeMorgan7s Theorems | |
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| Universality of NAND Gates and NOR Gates | |
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| Alternate Logic-Gate Representations | |
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| Which Gate Representation to Use | |
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| IEEE/ANSI Standard Logic Symbols | |
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| Summary of Methods to Describe Logic Circuits | |
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| Description Languages Versus Programming Languages | |
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| Implementing Logic Circuits with PLDs | |
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| HDL Format and Syntax | |
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| Intermediate Signals | |
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| Combinational Logic Circuits | |
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| Sum-of-Products Form | |
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| Simplifying Logic Circuits | |
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| Algebraic Simplification | |
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| Designing Combinational Logic Circuits | |
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| Karnaugh Map Method | |
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| Exclusive-OR and Exclusive-NOR Circuits | |
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| Parity Generator and Checker | |
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| Enable/Disable Circuits | |
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| Basic Characteristics of Digital ICs | |
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| Troubleshooting Digital Systems | |
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| Internal Digital IC Faults | |
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| External Faults | |
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| Troubleshooting Case Study | |
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| Programmable Logic Devices | |
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| Representing Data in HDL | |
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| Truth Tables Using HDL | |
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| Decision Control Structures in HDL | |
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| Flip-Flops and Related Devices | |
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| NAND Gate Latch | |
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| NOR Gate Latch | |
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| Troubleshooting Case Study | |
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| Digital Pulses | |
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| Clock Signals and Clocked Flip-Flops | |
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| Clocked S-R Flip-Flop | |
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| Clocked J-K Flip-Flop | |
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| Clocked D Flip-Flop | |
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| D Latch (Transparent Latch) | |
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| Asynchronous Inputs | |
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| IEEE/ANSI Symbols | |
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| Flip-Flop Timing Considerations | |
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| Potential | |