| |
| |
| (NOTE:Each chapter concludes with a Summary and Exercises.) | |
| |
| |
| About the Author | |
| |
| |
| Foreword | |
| |
| |
| Preface | |
| |
| |
| Acknowledgments | |
| |
| |
| |
| Basic Verilog Topics | |
| |
| |
| |
| Overview of Digital Design with Verilog HDL. Evolution of Computer-Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs | |
| |
| |
| |
| Hierarchical Modeling Concepts | |
| |
| |
| Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example | |
| |
| |
| |
| Basic Concepts | |
| |
| |
| Lexical Conventions. Data Types. System Tasks and Compiler Directives | |
| |
| |
| |
| Modules and Ports | |
| |
| |
| Modules. Ports. Hierarchical Names | |
| |
| |
| |
| Gate-Level Modeling | |
| |
| |
| Gate Types. Gate Delays | |
| |
| |
| |
| Dataflow Modeling | |
| |
| |
| Continuous Assignments. Delays. Expressions, Operators, and Operands. Operator Types. Examples | |
| |
| |
| |
| Behavioral Modeling | |
| |
| |
| Structured Procedures. Procedural Assignments. Timing Controls. Conditional Statements. Multiway Branching. Loops. Sequential and Parallel Blocks. Generate Blocks. Examples | |
| |
| |
| |
| Tasks and Functions | |
| |
| |
| Difference between Tasks and Functions. Tasks. Functions | |
| |
| |
| |
| Useful Modeling Techniques | |
| |
| |
| Procedural Continuous Assignments. Overriding Parameters. Conditional Compilation and Execution. Time Scales. Useful System Tasks | |
| |
| |
| |
| Advanced Verilog Topics | |
| |
| |
| |
| Timing and Delays | |
| |
| |
| Types of Delay Models. Path Delay Modeling. Timing Checks. Delay Back-Annotation | |
| |
| |
| |
| Switch Level Modeling | |
| |
| |
| Switching-Modeling Elements. Examples | |
| |
| |
| |
| User-Defined Primitives | |
| |
| |
| UDP basics. Combinational UDPs. Sequential UDPs. UDP Table Shorthand Symbols. Guidelines for UDP Design | |
| |
| |
| |
| Programming Language Interface | |
| |
| |
| Uses of PLI. Linking and Invocation of PLI Tasks. Internal Data Representation. PLI Library Routines | |
| |
| |
| |
| Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Synthesis Design Flow. Verification of the Gate-Level Netlist. Modeling Tips for Logic Synthesis. Example of Sequential Circuit Synthesis | |
| |
| |
| |
| Advanced Verification Techniques | |
| |
| |
| Traditional Verification Flow. Assertion Checking. Formal Verification | |
| |
| |
| |
| Appendices | |
| |
| |
| |
| Strength Modeling and Advanced Net Definitions Strength Levels | |
| |
| |
| Signal Contention. Advanced Net Types | |
| |
| |
| |
| List of PLI Routines Conventions | |
| |
| |
| Access Routines. Utility (tf_) Routines | |
| |
| |
| |
| List of Keywords, System Tasks and Compiler Directives Keywords | |
| |
| |
| System Tasks and Functions. Compiler Directives | |
| |
| |
| |
| Formal Syntax Definition Source Text. Declarations | |
| |
| |
| Primitive Instances. Module and Generated Instantiation | |
| |
| |
| UDP Declaration and Instantiation. Behavioral Statements | |
| |
| |
| Specify Section. Expressions. General | |
| |
| |
| |
| Verilog Tidbits | |
| |
| |
| |