See MIPS Run

ISBN-10: 1558604103
ISBN-13: 9781558604100
Edition: N/A
Authors: Dominic Sweetman
List price: $68.95
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Description: The versatile offspring of an extended family of multiple chip companies, today's MIPS chips are everywhere. They power everything from videogames, network routers, laser printers, set-top boxes, and high-performance workstations. This book brings  More...

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Book details

List price: $68.95
Publisher: Elsevier Science & Technology Books
Publication date: 2/9/1999
Binding: Paperback
Pages: 512
Size: 7.50" wide x 9.25" long x 1.00" tall
Weight: 1.892
Language: English

The versatile offspring of an extended family of multiple chip companies, today's MIPS chips are everywhere. They power everything from videogames, network routers, laser printers, set-top boxes, and high-performance workstations. This book brings together this extraordinary proliferation of form and functionality, offering embedded systems programmers and designers unique, eminently practical insights into MIPS. It covers how MIPS started, the principles at the root of the RISC revolution, the full details of the MIPS instruction set, and how these details together constitute a full operating system ready to be put to work in hundreds of ways. If you're programming embedded systems and need to understand the chips at the deepest level, or even if you're just curious, you're sure to find what you need in this book. It's all here, from the nuts and bolts of a programming reference to the big picture that only a true expert can deliver. So buy the book. Take it home. Step inside. And see MIPS run. * Written by an independent consultant whose business is understanding MIPS architecture and embedded systems programming. * Addresses the evolution of MIPS technology, giving you a solid foundation for successful designs and implementations. * Provides an in-depth, easy-to-use guide to the MIPS instruction set, including special attention to processor control and assembler mnemonics for every instruction. * Covers everything from MIPS I to MIPS IV, with appendices devoted to the optional MIPS 16 instruction set and V/MDMX.

Foreword
Preface
Style and Limits
Conventions
Acknowledgments
RISCs and MIPS
MIPS Architechture
Coprocessor 0: MIPS Processor Control
Caches for MIPS
Exceptions, Interrupts, and Initialization
Memory Management and the TLB
Floating-Point Support
Complete Guide to the MIPS Instruction Set
Assembler Language Programming
C Programming on MIPS
Portability Considerations and C Code
Software Examples
Appendix A Instruction Timing and Optimization
Appendix B Assembler Language Syntax
Appendix C Object Code
Appendix D Evolving MIPS
MIPS Glossary
References

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