Digital Integrated Circuits Analysis and Design

ISBN-10: 142006987X
ISBN-13: 9781420069877
Edition: 2nd 2009 (Revised)
Authors: John E. Ayers
List price: $125.95
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Description: Any textbook more than five years old simply won’t do in digital integrated circuits, as dynamic CMOS circuits  have emerged to dominate the field.  Providing a revised instructional text for engineers involved with Very Large Scale Integrated  More...

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Book details

List price: $125.95
Edition: 2nd
Copyright year: 2009
Publisher: CRC Press LLC
Publication date: 10/5/2009
Binding: Hardcover
Pages: 598
Size: 6.50" wide x 9.75" long x 1.50" tall
Weight: 2.134
Language: English

Any textbook more than five years old simply won’t do in digital integrated circuits, as dynamic CMOS circuits  have emerged to dominate the field.  Providing a revised instructional text for engineers involved with Very Large Scale Integrated Circuit design and fabrication, this second edition delves into the dramatic advances, including new applications and changes in the physics of operation made possible by relentless miniaturization.  Each chapter includes numerous worked examples, case studies and SPICE computer simulations. The book’s website offers supplementary material and more worked problems. Qualifying instructors will have access to a new instructor’s manual.

Preface
About the Author
Introduction
Historical Perspective and Moore's Law
Electrical Properties of Digital Integrated Circuits
Logic Function
Static Voltage Transfer Characteristics
Transient Characteristics
Fan-In and Fan-Out
Dissipation
Power Delay Product
Computer-Aided Design and Verification
Fabrication
Semiconductors and Junctions
The MOS Transistor
MOS Gate Circuits
Interconnect
Dynamic CMOS
Low-Power CMOS
Bistable Circuits
Memories
Input/Output and Interface Circuits
Practical Perspective
Summary
Exercises
References
Fabrication
Introduction
Basic CMOS Fabrication Sequence
Advanced Processing for High-Performance CMOS
Copper Metal
Metal Gates
High-? Gate Dielectric
Lithography and Masks
Layout and Design Rules
Minimum Line Widths and Spacings
Contacts and Vias
Testing and Yield
Packaging
Burn-In and Accelerated Testing
Practical Perspective
Summary
Exercises
References
Semiconductors and p-n Junctions
Introduction
Crystal Structure of Silicon
Energy Bands
Carrier Concentrations
Intrinsic Silicon
n-Type Silicon
p-Type Silicon
Current Transport
Carrier Continuity Equations
Poisson's Equation
The p-n Junction
Zero Bias (Thermal Equilibrium)77
Built-in Voltage V<sub>bi</sub>
Depletion Width W
Depletion Capacitance
Forward Bias Current
Short-Base n<sup>+</sup>-p Junction
Long-Base n<sup>+</sup>-p Junction
Reverse Bias
Reverse Breakdown
Metal-Semiconductor Junctions
SPICE Models
Practical Perspective
Summary
Exercises
References
The MOS Transistor
Introduction
The MOS Capacitor
Threshold Voltage
MOSFET Current-Voltage Characteristics
Linear Operation
Saturation Operation
Subthreshold Operation
Transit Time
Short-Channel MOSFETs
The Short-Channel Effect
Narrow-Channel Effect
Drain-Induced Barrier Lowering
Channel Length Modulation
Field-Dependent Mobility and Velocity Saturation
Transit Time in Short-Channel MOSFETs
MOSFET Design
MOSFET Capacitances
Oxide Capacitances
p-n Junction Capacitances
The Miller Effect
MOSFET Constant-Field Scaling
SPICE MOSFET Models
MOSFET Level 1 Model
Berkeley Short-Channel Insulated Gate Field Effect Transistor Model
BSIM1 Parameters
BSIM1 Threshold Voltage
BSIM1 Drain Current-Linear Region
BSIM1 Drain Current-Saturation Region
BSIM1 Drain Current-Subthreshold Region
Hand Calculations Related to the BSIM1
SPICE Demonstrations
Practical Perspective
Summary
Exercises
References
MOS Gate Circuits
Inverter Static Characteristics
Critical Voltages
Output High-Voltage V<sub>OH</sub>
Output Low-Voltage V<sub>OL</sub>
Input Low-Voltage V<sub>IL</sub>
Input High-Voltage V<sub>IH</sub>
Switching Threshold (Midpoint) Voltage V<sub>M</sub>
Dissipation
Propagation Delays
Fan-Out
NOR Circuits
NAND Circuits
Exclusive OR (XOR) Circuit
General Logic Design
Pass Transistor Circuits
SPICE Demonstrations
Practical Perspective
Summary
Exercises
Static CMOS
Introduction
Voltage Transfer Characteristic
Voltage Regime One: n-MOS Cutoff and p-MOS Linear
Voltage Regime Two: n-MOS Saturated and p-MOS Linear
Voltage Regime Three: Both MOSFETs Saturated
Voltage Regime Four: n-MOS Linear and p-MOS Saturated
Voltage Regime Five: n-MOS Linear and p-MOS Cutoff
Load Surface Analysis
Critical Voltages
Input Low-Voltage V<sub>IL</sub>
Switching Threshold V<sub>M</sub>
Input High-Voltage V<sub>IH</sub>
Crossover (Short-Circuit) Current
Current Regime One: n-MOS Cutoff
Current Regime Two: n-MOS Saturated
Current Regime Three: p-MOS Saturated
Current Regime Four: p-MOS Cutoff
Unified Expression for the Crossover Current
Effect of Threshold Voltages
Propagation Delays
High-to-Low Propagation Delay t<sub>PHL</sub>
Low-to-High Propagation Delay t<sub>PLH</sub>
Propagation Delay Design Equations
Propagation Delays in the Symmetric Inverter
Approximate Expressions for the Propagation Delays
Effect of the Input Rise and Fall Time
Inverter Rise and Fall Times
Fall Time
Rise Time
Effect of the Input Rise and Fall Time on Output Rise and Fall Time
Propagation Delays in Short-Channel CMOS
High-to-Low Propagation Delay t<sub>PHL</sub> in Short-Channel CMOS
Low-to-High Propagation Delay t<sub>PLH</sub> in Short-Channel CMOS
Comparison of the Short-Channel and Long-Channel Delay Equations
Propagation Delay Design Equations for Short-Channel CMOS
Power Dissipation
Capacitance Switching Dissipation
Short-Circuit Dissipation
Leakage Current Dissipation
Fan-Out
Circuit Delays as Functions of Fan-Out
CMOS Ring Oscillator
CMOS Inverter Design
CMOS NAND Circuits
Sizing of Transistors in a CMOS NAND Gate
Static Characteristics of the CMOS NAND Gate
Dynamic Characteristics of the CMOS NAND Gate
CMOS NOR Circuits
Other Logic Functions in CMOS
Transistor Sizing in CMOS AND-OR-INVERT Gates
74HC Series CMOS
Pseudo NMOS Circuits
Scaling of CMOS
Full Scaling of CMOS
Constant Voltage Scaling of CMOS
Latch-Up in CMOS
SPICE Demonstrations
Summary
Practical Perspective
Exercises
Interconnect
Introduction
Capacitance of Interconnect
Resistance of Interconnect
Inductance of Interconnect
Modeling Interconnect Delays
Lumped Capacitance Model
Distributed Models
Transmission Line Model
Crosstalk
Polysilicon Interconnect
SPICE Demonstrations
Practical Perspective
Summary
Exercises
References
Dynamic CMOS
Introduction
Rise Time
Fall Time
Charge Sharing
Charge Retention
Logic Design
Alternative Form Using a p-MOS Pull-Up Network
Cascading of Dynamic Logic Circuits
Domino Logic
Multiple-Output Domino Logic
Zipper Logic
Dynamic Pass Transistor Circuits
Logic "1" Transfer Delay t<sub>1</sub>
Logic "0" Transfer Delay t<sub>0</sub>
CMOS Transmission Gate Circuits
SPICE Demonstrations
Practical Perspective
Summary
Exercises
References
Low-Power CMOS
Introduction
Low-Voltage CMOS
Multiple Voltage CMOS
Dynamic Voltage Scaling
Active Body Biasing
Multiple-Threshold CMOS
Adiabatic Logic
Silicon-on-Insulator
SOI Technologies: SIMOX and Wafer Bonding
SOI MOSFETs: Fully Depleted or Partially Depleted
SOI for Low-Power CMOS
Practical Perspective
Summary
Exercises
References
Bistable Circuits
Introduction
Set-Reset Latch
SR Flip-Flop
JK Flip-Flops
Other Flip-Flops
Schmitt Triggers
CMOS Schmitt Trigger
SPICE Demonstrations
Practical Perspective
Summary
Exercises
References
Digital Memories
Introduction
Static Random Access Memory
CMOS SRAM Cell
NMOS SRAM Cell
SRAM Sense Amplifiers
Dynamic Random Access Memory
Read-Only Memory
NOR Read-Only Memory
NAND Read-Only Memory
Programmable Read-Only Memory
Erasable Programmable Read-Only Memory
Electrically Erasable Programmable Read-Only Memory
Flash Memory
Other Nonvolatile Memories
Access Times in Digital Memories
Row and Column Decoder Design
Practical Perspective
Summary
Exercises
References
Input/Output and Interface Circuits
Introduction
Input Electrostatic Discharge Protection
Input Enable Circuits
CMOS Transmission Gate
Regime One: n-MOS Linear and p-MOS Cutoff
Regime Two: n-MOS Linear and p-MOS Linear
Regime Three: n-MOS Cutoff and p-MOS Linear
Overall Characteristic of CMOS Transmission Gate
CMOS Output Buffers
Tri-State Outputs
Interface Circuits
High-Voltage CMOS to Low-Voltage CMOS
Low-Voltage CMOS to High-Voltage CMOS
SPICE Demonstrations
Summary
Practical Perspective
Exercises
References
List of Symbols
International System of Units
Unit Prefixes
Greek Alphabet
Physical Constants
Properties of Si and Ge at 300 K
Properties of SiO<sub>2</sub> at 300 K
Important Equations
Design Rules
p-n Junction Switching Transients
Bipolar and BiCMOS Circuits
Integrated Circuit Package
Index

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