| Determination of Defect Size Distributions Based on Electrical Measurements at a Novel Harp Test Structure | p. 1 |
| Yield Prediction using calibrated critical area modelling | p. 7 |
| Test structures for hillock growth, via filling and for measuring the quality of thin films | p. 11 |
| Electrical Linewidth Test Structures Fabricated in Mono-Crystalline Films for Reference-Material Applications | p. 16 |
| A digital test structure for simultaneous bird's beak length and misalignment measurement in polysilicon emitter bipolar technologies | p. 25 |
| Lateral Power MOSFET Low-Doped Drain (LDD) Misalignment Test Structure | p. 31 |
| Reference-Length Shortening by Kelvin Voltage Taps in Linewidth Test Structures Replicated in Mono-Crystalline Silicon Films | p. 35 |
| Optical Signal Injection for High-Speed Wafer Level Function Test of Integrated Circuits | p. 39 |
| On Wafer Noise Measurement Using Bipolar Transistor RF Test Structures | p. 43 |
| Flicker Noise Characterization of Polysilicon Resistors in Submicron BICMOS Technologies | p. 49 |
| A Proposal for Modeling Substrate Coupling in Si-MMIC's and its Experimental Verification up to 40 GHz | p. 52 |
| Digital Test Circuit Design and Optimization for AC Hot-Carrier Reliability Characterization and Model Calibration under Realistic High Frequency Stress Conditions | p. 56 |
| New Method for the Parameter Extraction in Si MOSFETs After Hot Carrier Injection | p. 63 |
| Optimization of via contact test structure for electro-migration | p. 67 |
| A Compact Monitoring Circuit for Real-Time On-Chip Diagnosis of Hot-Carrier Induced Degradation | p. 72 |
| An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution | p. 77 |
| A New Test Structure for Interconnect Capacitance Monitoring | p. 81 |
| Electrical Assessment of Planarisation for CMP | p. 85 |
| Measurement and Characterization of Multi-Layered Interconnect Capacitance for Deep Submicron VLSI Technology | p. 91 |
| Error Correction for Finite Semiconductor Resistivity in Kelvin Test Structures | p. 95 |
| GIDL-Induced Charge Injection for Characterization of Plasma Edge Damage in CMOS Devices | p. 99 |
| On the Oxide Thickness Extraction in Deep-Submicron Technologies | p. 105 |
| Improved Method for the Extraction of Oxide Charge Density and Centroid from the Current-Voltage Characteristic Shifts in a MOS Structure After Uniform Gate Stress | p. 111 |
| Integrated Test Circuit to Measure Polarization Characteristics of Ferroelectric Capacitors for Development of Mega-bit Scale FeRAM | p. 116 |
| Wire-Segment Holographic Test Structures for Statistical Interconnect Metrology | p. 121 |
| A New Technique and a Test Structure for Evaluating Vth Distribution of Flash Memory Cells | p. 127 |
| Performance Evaluation of CMOS Ring-Oscillators with Source/Drain Regions Fabricated by Asymmetric/Symmetric Ion-Implantation | p. 131 |
| A statistical method for the analysis of CMOS process fluctuations on dynamic performance | p. 137 |
| Design and Characterization of SiGe TFT Devices and Process using Stanford's Test Chip Design Environment | p. 143 |
| Issues on Short Circuits in Large On-Chip Power MOS-Transistors Using a Modified Checkerboard Test Structure | p. 146 |
| Test Structures for Characterising a Damascene CMP Interconnect Process | p. 151 |
| Novel Structure to Measure Emitter-Base Misalignment | p. 156 |
| Test Chip and Data Considerations for MOS Parameter Extraction | p. 159 |
| Test Structure and Methodology for Experimental Extraction of Threshold Voltage Shifts due to Quantum Mechanical Effects in MOS Inversion Layers | p. 165 |
| Characterisation of the Threshold Voltage Variation: a Test Chip and the Results | p. 169 |
| Test structure for mismatch characterization of MOS transistors in subthreshold regime | p. 173 |
| Test Structures for Investigation of Metal Coverage Effects on MOSFET Matching | p. 179 |
| Evaluation of hFE fluctuation of High-Performance IDP Emitter Transistors by Using Test Structures | p. 184 |
| New Approach for the Extraction of Gate Voltage Dependent Series Resistance and Channel Length Reduction in CMOS Transistors | p. 188 |
| A DC Voltage Capacitance Matching Tester | p. 194 |
| Separation of Intrinsic and Parasitic MOSFET Parameters Using A Multiple Built-In Kelvin Test Structure | p. 198 |
| Test Structures to Measure the Heat Capacity of CMOS Layer Sandwiches | p. 203 |
| Study of "On-chip" Measurement Methods of Thin Film Mechanical Properties for Micromachining | p. 209 |
| Test Structures Applied to the Rapid Prototyping of Sensors | p. 212 |
| Test Structures for the Evaluation of Air-Bridge Interconnection in GaAs IC's Fabrication Process | p. 219 |
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