Digital Design with CPLD Applications and VHDL

ISBN-10: 0766811603

ISBN-13: 9780766811607

Edition: 2001

Authors: Robert K. Dueck
List price: $226.95
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Book details

List price: $226.95
Copyright year: 2001
Publisher: Delmar Cengage Learning
Publication date: 6/28/2000
Binding: Hardcover
Pages: 896
Size: 8.87" wide x 1.12" long x 1.49" tall
Weight: 4.818
Language: English

Preface
Basic Principles of Digital Systems
Digital Versus Analog Electronics
Digital Logic Levels
The Binary Number System
Hexadecimal Numbers
Digital Waveforms
Logic Functions and Gates
Basic Logic Functions
Logic Switches and LED Indicators
Derived Logic Functions
DeMorgan's Theorems and Gate Equivalence
Enable and Inhibit Properties of Logic Gates
Integrated Circuit Logic Gates
Boolean Algebra and Combinational Logic
Boolean Expressions, Logic Diagrams and Truth Tables
Sum-of-Products (SOP) and Product-of-Sums (POS) Forms
Theorems of Boolean Algebra
Simplifying SOP and POS Expressions
Simplification by the Karnaugh Map Method
Introduction to PLDs and MAX+PLUS II
What is a PLD?
Programming PLDs using MAX+PLUS II
Graphic Design File
Compling MAX+PLUS II Files
Hierarchical Design
Text Design File (VHDL)
Creating a Physical Design
Combinational Logic Functions
Decoders
Encoders
Multiplexers
Demultiplexers
Magnitude Comparators
Parity Generators and Checkers
Digital Arithmetic and Arithmetic Circuits
Digital Arithmetic
Representing Signed Binary Numbers
Signed Binary Arithmetic
Hexadecimal Arithmetic
Numeric and Alphanumeric Codes
Binary Adders and Subtractors
BCD Adders
Carry Generation in MAX+PLUS II
Introduction to Sequential Logic
Latches
NAND/NOR Latches
Gated Latches
Edge-Triggered D Flip-Flops
Edge-Triggered JK Flip-Flops
Edge-Triggered T Flip-Flops
Timing Parameters
Introduction to Programmable Logic Architectures
Programmable Sum-of-Products Arrays
PAL Fuse Matrix and Combinational Outputs
PAL Outputs with Programmable Polarity
PAL Devices with Registered Outputs
Universal PAL and Generic Array Logic
MAX7000S CPLD
FLEX10K CPLD
Counters and Shift Registers
Basic Concepts of Digital Counters
Synchronous Counters
Design of Synchronous Counters
Programming Binary Counters in VHDL
Control Options for Synchronous Counters
Programming Presettable and Bidirectional Counters in VHDL
Shift Registers
Programming Shift Registers in VHDL
Shift Register Counters
State Machine Design
State Machines
State Machines With No Control Inputs
State Machines With Control Inputs
Switch Debouncer for a Normally Open Pushbutton Switch
Unused States in State Machines
Traffic Light Controller
Logic Gate Circuitry
Electrical Characteristics of Logic Gates
Propagation Delay
Fanout
Power Dissipation
Noise Margin
Interfacing TTL and CMOS Gates
Internal Circuitry of TTL gates
Internal Circuitry of CMOS Gates
TTL and CMOS Variations
Interfacing Analog and Digital Circuitry
Analog and Digital Signals
Digital-to-Analog Conversion
Analog-to-Digital Conversion
Data Acquisition
Memory Devices and Systems
Basic Memory Concepts
Random Access Read/Write Memory (RAM)
Read Only Memory (ROM)
Sequential Memory: FIFO and LIFO
Dynamic RAM Modules
Memory Systems
Altera UP-1 User's Guide
VHDL Language Reference
Data Sheets
CMOS Handling Precautions
EPROM/ROM Data for a Digital Function Generator
Answers to Selected Odd-Numbered Problems
Index
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