| |
| |
Preface | |
| |
| |
| |
Condensed Overview of Introductory Digital Logic Design | |
| |
| |
| |
Number Formats | |
| |
| |
| |
Combinational Logic | |
| |
| |
| |
Combinational Logic Devices | |
| |
| |
| |
Combinational Logic Circuit Design | |
| |
| |
| |
Sequential Logic | |
| |
| |
| |
Sequential Logic Devices | |
| |
| |
| |
Synchronous Sequential Circuit Design | |
| |
| |
| |
Hazards and Glitches | |
| |
| |
| |
Mestastability | |
| |
| |
| |
Digital Logic Design Using Hardware Description Languages | |
| |
| |
| |
Hardware description Languages | |
| |
| |
| |
Design Flow | |
| |
| |
| |
Synthesis | |
| |
| |
| |
Register Transfer Level Notation | |
| |
| |
| |
Logic Simulation | |
| |
| |
| |
Properties of Actual Circuits | |
| |
| |
| |
Introduction to VHDL and Test Benches | |
| |
| |
| |
Overview | |
| |
| |
| |
VHDL Basics | |
| |
| |
| |
Entity and Architecture | |
| |
| |
| |
Signals, Data, Types, Constants and Operators | |
| |
| |
| |
Libraries and Packages | |
| |
| |
| |
Structural and Behavioral | |
| |
| |
| |
Testing and the Test Bench | |
| |
| |
| |
Manufacturing Testing | |
| |
| |
| |
Functional Testing | |
| |
| |
| |
Test Benches | |
| |
| |
| |
VHDL Test Bench | |
| |
| |
| |
More Advanced VHDL Concepts | |
| |
| |
| |
Concurrent and Sequential VHDL | |
| |
| |
| |
Variables and Signals | |
| |
| |
| |
Delay Modeling | |
| |
| |
| |
Attributes | |
| |
| |
| |
Procedures and Functions | |
| |
| |
| |
Generics and Modeling a Bidirectional Bus | |
| |
| |
| |
Construction of Complete VHDL Programs | |
| |
| |
| |
Combinational Logic Circuits | |
| |
| |
| |
Sequential Logic Circuits | |
| |
| |
| |
Behavioral Modeling of More Complex Circuits | |
| |
| |
| |
High-Level VHDL Coding for Synthesis | |
| |
| |
| |
Register Transfer Level Notation | |
| |
| |
| |
Combinational Logic Synthesis | |
| |
| |
| |
Using Concurrent Signal Assignment Statements for Combinational Logic | |
| |
| |
| |
Using Process Blocks for Combinational Logic | |
| |
| |
| |
Complex Combinational Logic Example | |
| |
| |
| |
Sequential Logic Synthesis | |
| |
| |
| |
Synthesis Heuristics | |
| |
| |
| |
Synthesis Using a Commercial Tool | |
| |
| |
| |
High-Level VHDL Coding | |
| |
| |
| |
State Machine Design | |
| |
| |
| |
Manual State Machine Design | |
| |
| |
| |
Pseudocode | |
| |
| |
| |
RTL Program | |
| |
| |
| |
Datapath | |
| |
| |
| |
State Diagram | |
| |
| |
| |
Control Logic | |
| |
| |
| |
State Machine Design Using ASM Charts | |
| |
| |
| |
Automatic Synthesis-Based State Machine Design | |
| |
| |
| |
Automatic Synthesis-Based Design Procedure | |
| |
| |
| |
Algorithm to HDL Code Conversion | |
| |
| |
| |
Design Example: Vending Machine | |
| |
| |
| |
Automatic State Machine Design for a Vending Machine | |
| |
| |
| |
Manual State Machine Design for a Vending Machine | |
| |
| |
| |
Timing Diagram | |
| |
| |
| |
Correspondence Between Automatic and Manual Designs | |
| |
| |
| |
Design Example: LCD Controller | |
| |
| |
| |
Target LCD Module | |
| |
| |
| |
VHDL Solution | |
| |
| |
| |
FPGA and Other Programmable Logic Devices | |
| |
| |
| |
Programmable Logic Devices | |
| |
| |
| |
Circuit Customization | |
| |
| |
| |
Programmable Logic Arrays | |
| |
| |
| |
Programmable Read Only Memories | |
| |
| |
| |
Programmable AND-Array Logic | |
| |
| |
| |
Field Programmable Gate Arrays | |
| |
| |
| |
Gate Arrays | |
| |
| |
| |
FPGA Overview | |
| |
| |
| |
Xilinx FPGA Example | |
| |
| |
| |
FPGA Configuration | |
| |
| |
| |
Xilinx Spartan-II FPGA Configuration Example | |
| |
| |
| |
Boundary Scan | |
| |
| |
| |
Design of a USB Protocol Analyzer | |
| |
| |
| |
Overview of USB Full-Speed Mode | |
| |
| |
| |
Packet Transfer Protocol | |
| |
| |
| |
Initialization Sequence | |
| |
| |
| |
Physical Layer Interface | |
| |
| |
| |
USB Packets | |
| |
| |
| |
Cyclic Redundancy Checks | |
| |
| |
| |
Observation of Actual USB Signals | |
| |
| |
| |
Design Overview | |
| |
| |
| |
State Machine | |
| |
| |
| |
Subcircuit Partitioning | |
| |
| |
| |
VHDL Solution | |
| |
| |
| |
Digital Phase Locked Loop | |
| |
| |
| |
NRZI-to-Binary Converter | |
| |
| |
| |
CRC Checker Subcircuits | |
| |
| |
| |
Packet ID Recognizer | |
| |
| |
| |
State Machine Subcircuit | |
| |
| |
| |
Top-Level Circuit | |
| |
| |
| |
Test Bench Code for Entire Circuit | |
| |
| |
| |
Simulation Results | |
| |
| |
| |
Design of Fast Arithmetic Units | |
| |
| |
| |
Adder Designs | |
| |
| |
| |
Ripple Carry adder | |
| |
| |
| |
Carry Lookahead Adder | |
| |
| |
| |
Carry Save Adder | |
| |
| |
| |
Multiplier Designs | |
| |
| |
| |
Combinational Multiplier | |
| |
| |
| |
Sequential Multiplier | |
| |
| |
| |
Fast Multiplication | |
| |
| |
| |
Multiply-Accumulate Units | |
| |
| |
| |
Pipelined Functional Units | |
| |
| |
| |
Introduction to Pipelining | |
| |
| |
| |
Pipelined Multiply-Accumulate Units | |
| |
| |
| |
HDL Implementations | |
| |
| |
| |
HDL Implementation Overview | |
| |
| |
| |
HDL Design for a Pipelined Multiply-Accumulate Unit | |
| |
| |
| |
Test Bench and Simulation Results | |
| |
| |
| |
Design of a Pipelined RISC Microprocessor | |
| |
| |
| |
Introduction to Microprocessors | |
| |
| |
| |
Reduced Instruction Set C | |