Computer Architecture and Organization An Integrated Approach

ISBN-10: 0471733881

ISBN-13: 9780471733881

Edition: 2007

List price: $219.95 Buy it from $20.33
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Description: Taking an integrated approach, this book addresses the great diversity of areas that a computer professional must know Exposes the inner workings of the modern digital computer at a level that demystifies what goes on inside the machine Focuses on the instruction set architecture (ISA), the coverage of network-related topics, and the programming methodology Each topic is discussed in the context of the entire machine and how the implementation affects behavior Describes network architectures, focusing on both local area networks and wide area networks

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Book details

List price: $219.95
Copyright year: 2007
Publisher: John Wiley & Sons, Incorporated
Publication date: 3/16/2007
Binding: Hardcover
Pages: 544
Size: 7.50" wide x 9.50" long x 1.00" tall
Weight: 2.046
Language: English

Preface
Introduction
A Brief History of Computing
The Von Neumann Model
The System Bus Model
Levels of Machines
Upward Compatibility
The Levels
A Typical Computer System
Role of the Network
Organization of the Book
Case Study: What Happened to Supercomputers?
Data Representation
Fixed-Point Numbers
Range and Precision in Fixed-Point Numbers
The Associative Law of Algebra Does Not Always Hold in Computers
Radix Number Systems
Conversions Among Radices
An Early Look at Computer Arithmetic
Signed Fixed-Point Numbers
Floating-Point Numbers
Range and Precision in Floating-Point Numbers
Normalization and the Hidden Bit
Representing Floating-Point Numbers in the Computer-Preliminaries
Error in Floating-Point Representations
The IEEE 754 Floating-Point Standard
Case Study: Patriot Missile Defense Failure Caused by Loss of Precision
Character Codes
The ASCII Character Set
The EBCDIC Character Set
The Unicode Character Set
Arithmetic
Fixed-Point Addition and Subtraction
Two's Complement Addition and Subtraction
Sign Extension
Hardware Implementation of Adders and Subtractors
One's Complement Addition and Subtraction
Fixed-Point Multiplication and Division
Unsigned Multiplication
Unsigned Division
Signed Multiplication and Division
Floating-Point Arithmetic
Floating-Point Addition and Subtraction
Floating-Point Multiplication and Division
High-Performance Arithmetic
High-Performance Addition
High-Performance Multiplication
High-Performance Division
Residue Arithmetic
The Instruction Set Architecture
Hardware Components of the Instruction Set Architecture
The System Bus Model Revisited
Memory
The CPU
ARC, A RISC Computer
ARC Memory
ARC Registers
ARC Assembly Language Format
The ARC Instruction Set
ARC Instruction Formats
SPARC and ARC Data Formats
ARC Instruction Descriptions
Pseudo-Operations
Synthetic Instructions
Examples of Assembly Language Programs
Variations in Machine Architectures and Addressing
Performance of Instruction Set Architectures
Accessing Data in Memory-Addressing Modes
Subroutine Linkage and Stacks
Input and Output in Assembly Language
Case Study: The Java Virtual Machine ISA
Datapath and Control
Basics of the Microarchitecture
The Datapath
Datapath Overview
The Control Section-Microprogrammed
Timing
Developing the Microprogram
Traps and Interrupts
Nanoprogramming
The Control Section-Hardwired
Case Study: The VHDL Hardware Description Language
Background
What is VHDL?
A VHDL Specification of the Majority Function
Nine-Value Logic System
Case Study: What Happens When a Computer Boots Up?
Languages and the Machine
The Compilation Process
Steps in Compilation
The Compiler Mapping Specification
How the Compiler Maps the Three Instruction Classes into Assembly Code
Data Movement
Arithmetic Instructions
Program Control Flow
The Assembly Process
Assembly and Two-Pass Assemblers
Assembly and the Symbol Table
Final Tasks of the Assembler
Programs for Embedded vs. Virtual Memory Systems
Linking and Loading
Linking
Resolving External References
Loading
Macros
Quantitative Analyses of Program Execution
Quantitative Performance Analysis
From CISC to RISC
Pipelining the Datapath
Arithmetic, Branch, and Load-Store Instructions
Pipelining Instructions
Keeping the Pipeline Filled
Overlapping Register Windows
Low-Power Coding
Memory
The Memory Hierarchy
Random-Access Memory
Memory Chip Organization
Constructing Large RAMs From Small RAMs
Commercial Memory Modules
Read-Only Memory
Flash Memory
Case Study: Rambus Memory
Cache Memory
Associative Mapped Cache
Direct-Mapped Cache
Set-Associative Mapped Cache
Cache Performance
Hit Ratios and Effective Access Times
Multilevel Caches
Cache Management
Cache Coherency
Virtual Memory
Overlays
Paging
Segmentation
Protection
Fragmentation
The Translation Lookaside Buffer
Putting It All Together
Advanced Topics
Content-Addressable (Associative) Memories
Case Study: Associative Memory in Routers
Case Study: The Intel Pentium 4 Memory System
Buses and Peripherals
Parallel Bus Architectures
Bus Structure, Protocol, and Control
Bus Clocking
The Synchronous Bus
The Asynchronous Bus
Bus Arbitration-Masters and Slaves
Bridge-Based Bus Architectures
Internal Communication Methodologies
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)
Case Study: Communication on the Intel Pentium Architecture
System Clock, Bus Clock, and Bus Speeds
Address, Data, Memory, and I/O Capabilities
Data Words Have Soft Alignment
Bus Cycles in the Pentium family
Memory Read and Write Bus Cycles
The Burst Read Bus Cycle
Bus Hold for Request by Bus Master
Data Transfer Rates
Serial Bus Architectures
RS-232
Universal Serial Bus (USB)
Firewire
Mass Storage
Magnetic Disks
Magnetic Tape
Optical Disks
RAID-Redundant Arrays of Inexpensive Disks
Input Devices
Keyboards
Tablets
Mice and Trackballs
Touch-Sensitive Pen-Based Display
Joysticks
Output Devices
Laser Printers
Video Displays
Liquid Crystal Displays (LCDs)
Case Study: Graphics Processing Unit
Case Study: How a Virus Infects a Machine
Networking and Communication
A Few Modulation Schemes
Transmission Media
Two-Wire Open Lines
Twisted-Pair Lines
Coaxial Cable
Optical Fiber
Satellites
Terrestrial Microwave
Radio
Error Detection and Correction
Bit Error Rate Defined
Hamming Codes
Vertical Redundancy Checking
Cyclic Redundancy Checking
Networking and Network Device Architectures
The OSI Model
Topologies
Ethernet
Hubs, Bridges, Switches, Routers, and Gateways
Storage Area Networks
Case Study: Cisco Router Architecture
Advanced Computer Architecture
Parallel Architecture
Measuring Performance
The Flynn Taxonomy
Interconnection Networks
Mapping an Algorithm Onto a Parallel Architecture
Superscalar Machines and the PowerPC
Instruction Set Architecture of the PowerPC
Hardware Architecture of the PowerPC
VLIW Machines, and the Itanium
Case Study: The Intel IA-64 (Itanium) Architecture
Background-the 80x86 CISC Architecture
The Itanium: an Epic Architecture
Case Study: Extensions to the Instruction Set-The Intel MMX/SSEX and Motorola AltiVec SIMD Instructions
Background
The Base Architectures
VECTOR Registers
Vector Arithmetic Operations
Vector Compare Operations
Case Study Summary
Programmable Logic Devices and Custom ICs
The Role of CAD Tools in PLD Design
PLAS and PALS
Complex Programmable Logic Devices
Field-Programmable Gate Arrays
Application-Specific Integrated Circuits
Unconventional Architectures
DNA Computing
Quantum Computing
Multi-valued Logic
Neural Networks
Digital Logic
Introduction
Combinational Logic
Truth Tables
Logic Gates
Electronic Implementation of Logic Gates
Tri-State Buffers
Properties of Boolean Algebra
The Sum-of-Products Form and Logic Diagrams
The Product-of-Sums Form
Positive vs. Negative Logic
The Data Sheet
Digital Components
Levels of Integration
Multiplexers
Demultiplexers
Decoders
Priority Encoders
Programmable Logic Arrays
Sequential Logic
The S-R Flip-Flop
The Clocked S-R Flip-Flop
The D Flip-Flop and the Master-Slave Configuration
J-K and T Flip-Flops
Design of Finite State Machines
Mealy vs. Moore Machines
Registers
Counters
Reduction of Combinational Logic and Sequential Logic
Reduction of Two-Level Expressions
The Algebraic Method
The K-Map Method
The Tabular Method
Logic Reduction: Effect on Speed and Performance
State Reduction
Using ARCTools
Introduction
Accessing and Launching ARCTools
Launching ARCTools
The ARC Assembler
Loading, Assembling, and Examining a File
Saving Files
Loading Files into the Simulator
The ARC Simulator
Instructions and Pseudo Instructions Recognized by ARCTools
Instructions-Actual, Synthetic, and Pseudo
The Macroprocessor
Measuring Program Performance
The TimeModel configuration Editor
Memory/IO Parameters
TimeModel's Statistics Window
The Cache Simulator View
Index
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