Computer Systems Organization and Architecture

ISBN-10: 0201612534
ISBN-13: 9780201612530
Edition: 2001
List price: $181.20
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Description: This book provides up-to-date coverage of fundamental concepts for the design of computers and their subsystems. It presents material with a serious but easy-to-understand writing style that makes it accessible to readers without sacrificing  More...

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Book details

List price: $181.20
Copyright year: 2001
Publisher: Addison Wesley
Publication date: 10/20/2000
Binding: Hardcover
Pages: 584
Size: 7.50" wide x 9.00" long x 1.00" tall
Weight: 2.618
Language: English

This book provides up-to-date coverage of fundamental concepts for the design of computers and their subsystems. It presents material with a serious but easy-to-understand writing style that makes it accessible to readers without sacrificing important topics. The book emphasizes a finite state machine approach to CPU design, which provides a strong background for reader understanding. It forms a solid basis for readers to draw upon as they study this material and in later engineering and computer science practice. The book also examines the design of computer systems, including such topics as memory hierarchies, input/output processing, interrupts, and direct memory access, as well as advanced architectural aspects of parallel processing.To make the material accessible to beginners, the author has included two running examples of increasing complexity: the Very Simple CPU, which contains four instruction sets and shows very simple CPU design; and the Relatively Simple CPU which contains 16 instruction sets and adds enough complexity to illustrate more advanced concepts. Each chapter features a real-world machine on which the discussed organization and architecture concepts are implemented.This book is designed to teach computer organization/architecture to engineers and computer scientists.

Digital Logic and Finite State Machines
Digital Logic Fundamentals
Boolean Algebra
Basic Functions
Manipulating Boolean Functions
Basic Combinatorial Logic
More Complex Combinatorial Components
Adders and Subtracters
Combinatorial Circuit Designs
BCD to 7-segment Decoder
Data Sorter
Practical Perspective: Why LED's Are Usually Active Low
Basic Sequential Components
More Complex Sequential Components
Shift Registers
Real World Example: Programmable Logic Devices
Historical Perspective: Digital Circuit Implementation
Introduction to Finite State Machines
State Diagrams and State Tables
Historical Perspective: Finite State Machine and Microprocessors
Mealy and Moore Machines
Designing State Diagrams
Modulo 6 Counter
String Checker
Toll Booth Controller
Practical Perspective: Different Models For The Same Problem
From State Diagram to Implementation
Assigning State Values
Mealy and Moore Machine Implementations
Generating the Next State
Generating System Outputs
An Alternative Design
The Eight-State String Checker
Real World Example: Practical Considerations
Unused States
Asynchronous Designs
Machine Conversion
Computer Organization and Architecture
Instruction Set Architectures
Levels of Programming Languages
Language Categories
Compiling and Assembling Programs
Practical Perspective: Java Applets--A Different Way of Processing Programs
Assembly Language Instructions
Instruction Types
Data Types
Addressing Modes
Instruction Formats
Instruction Set Architecture Design
A Relatively Simple Instruction Set Architecture
Real World Example: The 8085 Microprocessor Instruction Set Architecture
The 8085 Microprocessor Register Set
Historical Perspective: Intel's Early Microprocessors
The 8085 Microprocessor Instruction Set
A Simple 8085 Program
Analyzing the 8085 Instruction Set Architecture
Introduction to Computer Organization
Basic Computer Organization
System Buses
Instruction Cycles
Practical Perspective: The Peripheral Component Interconnect Bus
CPU Organization
Memory Subsystem Organization and Interfacing
Types of Memory
Internal Chip Organization
Memory Subsystem Configuration
Historical Perspective: The von Neumann and Harvard Architectures
Multibyte Data Organization
Beyond the Basics
I/O Subsystem Organization and Interfacing
A Relatively Simple Computer
Real World Example: An 8085-based Computer
Historical Perspective: The Sojourner Rover
Register Transfer Languages
Micro-Operations and Register Transfer Language
Using RTL to Specify Digital Systems
Specification of Digital Components
Specification and Implementation of Simple Systems
More Complex Digital Systems and RTL
Modulo 6 Counter
Toll Booth Controller
Real World Example: VHDL-VHSIC Hardware Description Language
Practical Perspective: Hardware Description Languages
VHDL Syntax
VHDL Design with a High Level of Abstraction
VHDL Design with a Low Level of Abstraction
Practical Perspective: Some Advanced Capabilities of VHDL
CPU Design
Specifying a CPU
Design and Implementation of a Very Simple CPU
Specifications for a Very Simple CPU
Fetching Instructions from Memory
Practical Perspective: Why a CPU Increments PC During the Fetch Cycle
Decoding Instructions
Executing Instructions
Establishing Required Data Paths
Design of a Very Simple ALU
Designing the Control Unit Using Hardwired Control
Design Verification
Design and Implementation of a Relatively Simple CPU
Specifications for a Relatively Simple CPU
Fetching and Decoding Instructions
Executing Instructions
Establishing Data Paths
Design of a Relatively Simple ALU
Designing the Control Unit Using Hardwired Control
Design Verification
Shortcomings of the Simple CPUs
More Internal Registers and Cache
Historical Perspective: Storage in Intel Microprocessors
Multiple Buses Within the CPU
Pipelined Instruction Processing
Larger Instruction Sets
Subroutines and Interrupts
Real World Example: Internal Architecture of the 8085 Microprocessor
Microsequencer Control Unit Design
Basic Microsequencer Design
Microsequencer Operations
Microinstruction Formats
Design and Implementation of a Very Simple Microsequencer
The Basic Layout
Generating the Correct Sequence and Designing the Mapping Logic
Generating the Micro-Operations Using Horizontal Microcode
Generating the Micro-Operations Using Vertical Microcode
Practical Perspective: Nanoinstructions
Directly Generating the Control Signals from the Microcode
Design and Implementation of a Relatively Simple Microsequencer
Modifying the State Diagram
Designing the Sequencing Hardware and Microcode
Completing the Design Using Horizontal Microcode
Reducing the Number of Microinstructions
Microcode Jumps
Microprogrammed Control vs. Hardwired Control
Complexity of the Instruction Set
Ease of Modification
Clock Speed
Real World Example: A (Mostly) Microcoded CPU: The Pentium Processor
Historical Perspective: How the Pentium Got Its Name
Computer Arithmetic
Unsigned Notation
Addition and Subtraction
Signed Notation
Signed-Magnitude Notation
Signed-Two's Complement Notation
Binary Coded Decimal
BCD Numeric Format
Addition and Subtraction
Multiplication and Division
Specialized Arithmetic Hardware
Historical Perspective: Coprocessors
Lookup Tables
Historical Perspective: The Pentium Floating Point Bug
Wallace Trees
Floating Point Numbers
Numeric Format
Numeric Characteristics
Addition and Subtraction
Multiplication and Division
Real World Example: The IEEE 754 Floating Point Standard
Denormalized Values
Memory Organization
Hierarchical Memory Systems
Cache Memory
Associative Memory
Cache Memory with Associative Mapping
Cache Memory with Direct Mapping
Cache Memory with Set-Associative Mapping
Practical Perspective: Mapping Strategies in Current CPUs
Replacing Data in the Cache
Writing Data to the Cache
Cache Performance
Virtual Memory
Memory Protection
Beyond the Basics of Cache and Virtual Memory
Beyond the Basics of Cache Memory
Practical Perspective: Cache Hierarchy in the Itanium Microprocessor
Beyond the Basics of Virtual Memory
Real World Example: Memory Management in a Pentium/Windows Personal Computer
Input/Output Organization
Asynchronous Data Transfers
Source-Initiated Data Transfer
Destination-Initiated Data Transfer
Programmed I/O
New Instructions
New Control Signals
New States and RTL Code
Modify the CPU Hardware for the New Instruction
Make Sure Other Instructions Still Work
Transferring Data Between the CPU and I/O Devices
Types of Interrupts
Processing Interrupts
Interrupt Hardware and Priority
Implementing Interrupts Inside the CPU
Direct Memory Access
Incorporating Direct Memory Access (DMA) into a Computer System
DMA Transfer Modes
Modifying the CPU to Work with DMA
I/O Processors
Practical Perspective: The i960 I/O Processor with Built-in DMA
Serial Communication
Serial Communication Basics
Universal Asynchronous Receiver/Transmitters (UARTs)
Real World Example: Serial Communication Standards
The RS-232-C Standard
Practical Perspective: The RS-422 Serial Standard
The Universal Serial Bus Standard
Advanced Topics
Reduced Instruction Set Computing
RISC Rationale
Fixed Length Instructions
Limited Loading and Storing Instructions Access Memory
Fewer Addressing Modes
Instruction Pipeline
Practical Perspective: Addressing Modes in the PowerPC 750 RISC CPU
Large Number of Registers
Hardwired Control Unit
Delayed Loads and Branches
Speculative Execution of Instructions
Optimizing Compiler
Separate Instruction and Data Streams
RISC Instruction Sets
Instruction Pipelines and Register Windows
Instruction Pipelines
Register Windowing and Renaming
Practical Perspective: Register Windowing and Register Renaming in Real-World CPUs
Instruction Pipeline Conflicts
Data Conflicts
Branch Conflicts
Real World Example: The Itanium Microprocessor
Introduction to Parallel Processing
Parallelism in Uniprocessor Systems
Organization of Multiprocessor Systems
Flynn's Classification
System Topologies
MIMD System Architectures
Practical Perspective: The World's Largest Multicomputer?
Practical Perspective: The Blue Gene Computer
Communication in Multiprocessor Systems
Fixed Connections
Reconfigurable Connections
Routing on Multistage Interconnection Networks
Memory Organization in Multiprocessor Systems
Shared Memory
Cache Coherence
Multiprocessor Operating Systems and Software
Parallel Algorithms
Parallel Bubble Sort
Parallel Matrix Multiplication
Alternative Parallel Architectures
Dataflow Computing
Systolic Arrays
Neural Networks

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