Modern VLSI Design IP-Based Design

ISBN-10: 0137145004
ISBN-13: 9780137145003
Edition: 4th 2009
Authors: Wayne Wolf
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Description: The Number 1 VLSI Design Guide-Now Fully Updated for IP-Based Design and the Newest Technologies Modern VLSI Design, Fourth Edition, offers authoritative, up-to-the-minute guidance for the entire VLSI design process-from architecture and logic  More...

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Book details

List price: $120.00
Edition: 4th
Copyright year: 2009
Publisher: Prentice Hall PTR
Publication date: 12/21/2008
Binding: Hardcover
Pages: 656
Size: 7.00" wide x 9.50" long x 1.50" tall
Weight: 2.442
Language: English

The Number 1 VLSI Design Guide-Now Fully Updated for IP-Based Design and the Newest Technologies Modern VLSI Design, Fourth Edition, offers authoritative, up-to-the-minute guidance for the entire VLSI design process-from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for todayrsquo;s newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds. Coverage includes All-new material on IP-based design Extensive new coverage of networks-on-chips New coverage of using FPGA fabrics to improve design flexibility New material on image sensors, busses, Rentrsquo;s Rule, pipelining, and more Updated VLSI technology parameters reflecting the latest advances Revised descriptions of HDLs and other VLSI design tools Advanced techniques for overcoming bottlenecks and reducing crosstalk Low-power design techniques for enhancing reliability and extending battery life Testing solutions for every level of abstraction, from circuits to architecture Revamped end-of-chapter problems that fully reflect todayrsquo;s VLSI design challenges Wolf introduces a top-down, systematic design methodology that begins with high-level models, extends from circuits to architecture, and facilitates effective testing. Along the way, he brings together all the skills VLSI design professionals will need to create tomorrowrsquo;s state-of-the-art devices.

Wayne Wolf is Professor, Rhesea "Ray" P. Farmer Distinguished Chair in Embedded Computing, and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. Before joining Georgia Tech, he was with Princeton University and AT&T Bell Laboratories in Murray Hill, New Jersey. He received his B.S., M.S., and Ph.D. in electrical engineering from Stanford University. He is well known for his research in the areas of hardware/software co-design, embedded computing, VLSI CAD, and multimedia computing systems. He is a fellow of the IEEE and ACM. He co-founded several conferences in the area, including CODES, MPSoC, and Embedded Systems Week. He was founding co-editor-in-chief of Design Automation for Embedded Systems and founding editor-in-chief of ACM Transactions on Embedded Computing Systems. He has received the ASEE Frederick E. Terman Award and the IEEE Circuits and Society Education Award. He is also series editor of the Morgan Kaufmann Series in Systems on Silicon.

Preface to the Fourth Edition
Preface to the Third Edition
Preface to the Second Edition
Preface
About the Author
Digital Systems and VLSI
Why Design Integrated Circuits?
Integrated Circuit Manufacturing
CMOS Technology
Integrated Circuit Design Techniques
IP-Based Design
A Look into the Future
Summary
References
Problems
Fabrication and Devices
Introduction
Fabrication Processes
Transistors
Wires and Vias
Fabrication Theory and Practice
Reliability
Layout Design and Tools
References
Problems
Logic Gates
Introduction
Combinational Logic Functions
Static Complementary Gates
Switch Logic
Alternative Gate Circuits
Low-Power Gates
Delay through Resistive Interconnect
Delay through Inductive Interconnect
Design-for-Yield
Gates as IP
References
Problems
Combinational Logic Networks
Introduction
Standard Cell-Based Layout
Combinational Network Delay
Logic and Interconnect Design
Power Optimization
Switch Logic Networks
Combinational Logic Testing
References
Problems
Sequential Machines
Introduction
Latches and Flip-Flops
Sequential Systems and Clocking Disciplines
Performance Analysis
Clock Generation
Sequential System Design
Power Optimization
Design Validation
Sequential Testing
References
Problems
Subsystem Design
Introduction
Combinational Shifters
Adders
ALUs
Multipliers
High-Density Memory
Image Sensors
Field-Programmable Gate Arrays
Programmable Logic Arrays
Buses and Networks-on-Chis
Data Paths
Subsystems as IP
References
Problems
Floorplanning
Introduction
Floorplanning Methods
Global Interconnect
Floorplan Design
Off-Chip Connections
References
Problems
Architecture Design
Introduction
Hardware Description Languages
Register-Transfer Design
Pipelining
High-Level Synthesis
Architectures for Low Power
GALS Systems
Architecture Testing
IP Components
Design Methodologies
Multiprocessor System-on-Chip Design
References
Problems
A Chip Designer's Lexicon
Hardware Description Languages
Introduction
Verilog
VHDL
References
Index

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