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| (Note:Each chapter begins with an Outline, Objectives, and an Introduction, and concludes with a Summary, Glossary, Problems, Schematic Interpretation Problems, Electronics Workbench Exercises, and Answers to Review Questions.) | |
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| Number Systems and Codes | |
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| Digital Versus Analog | |
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| Digital Representations of Analog Quantities | |
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| Decimal Numbering System (Base 10) | |
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| Binary Numbering System (Base 2) | |
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| Decimal-to-Binary Conversion | |
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| Octal Numbering System (Base 8) | |
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| Octal Conversions | |
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| Hexadecimal Numbering System (Base 16) | |
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| Hexadecimal Conversions | |
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| Binary-Coded-Decimal System | |
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| Comparison of Numbering Systems | |
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| The ASCII Code | |
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| Applications of the Numbering Systems | |
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| Digital Electronic Signals and Switches | |
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| Digital Signals | |
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| Clock Waveform Timing | |
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| Serial Representation | |
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| Parallel Representation | |
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| Switches in Electronic Circuits | |
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| A Relay as a Switch | |
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| A Diode as a Switch | |
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| A Transistor as a Switch | |
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| The TTL Integrated Circuit | |
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| MultiSIM Simulation of Switching Circuits | |
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| The CMOS Integrated Circuit | |
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| Surface-Mount Devices | |
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| Basic Logic Gates | |
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| The AND Gate | |
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| The OR Gate | |
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| Timing Analysis | |
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| Enable and Disable Functions | |
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| Using IC Logic Gates | |
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| Introduction to Troubleshooting Techniques | |
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| The Inverter | |
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| The NAND Gate | |
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| The NOR Gate | |
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| Logic Gate Waveform Generation | |
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| Using IC Logic Gates | |
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| Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols | |
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| Programmable Logic Devices: Altera and Xilinx CPLDs and FPGAs | |
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| PLD Design Flow | |
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| PLD Architecture | |
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| Using PLDs to Solve Basic Logic Designs | |
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| CPLD Problems | |
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| Boolean Algebra and Reduction Techniques | |
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| Combinational Logic | |
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| Boolean Algebra Laws and Rules | |
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| Simplification of Combinational Logic Circuits Using Boolean Algebra | |
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| De Morgan's Theorem | |
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| The Universal Capability of NAND and NOR Gates | |
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| AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions | |
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| Karnaugh Mapping | |
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| System Design Applications | |
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| CPLD Design Applications | |
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| CPLD Problems | |
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| Exclusive-OR and Exclusive-NOR Gates | |
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| The Exclusive-OR Gate | |
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| The Exclusive-NOR Gate | |
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| Parity Generator/Checker | |
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| System Design Applications | |
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| CPLD Design Applications | |
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| CPLD Problems | |
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| Arithmetic Operations and Circuits | |
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| Binary Arithmetic | |
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| Two's-Complement Representation | |
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| Two's-Complement Arithmetic | |
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| Hexadecimal Arithmetic | |
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| BCD Arithmetic | |
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| Arithmetic Circuits | |
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| Four-Bit Full-Adder ICs | |
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| System Design Applications | |
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| Arithmetic/Logic Units | |
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| CPLD Design Applications | |
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| CPLD Problems | |
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| Code Converters, Multiplexers, and Demultiplexers | |
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| Comparators | |
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| Decoding | |
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| Encoding | |
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| Code Converters | |
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| Multiplexers | |
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| Demultiplexers | |
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| System Design Applications | |
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| CPLD Design Applications | |
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| CPLD Problems | |
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| Logic Families and Their Characteristics | |
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| The TTL Family | |
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| TTL Voltage and Current Ratings | |
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| Other TTL Considerations | |
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| Improved TTL Series | |
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| The CMOS Family | |
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| Emitter-Coupled Logic | |
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| Comparing Logic Families | |
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| Interfacing Logic Families | |
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| Flip-Flops and Registers | |
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| S-RFlip-Flop | |
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| GatedS-RFlip-Flop | |
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| GatedDFlip-Flop | |
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| Integrated-Circuit | |