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| Verilog Design in the Real World | |
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| Trivial Overheat Detector Example | |
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| Synthesizable Verilog Elements | |
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| Verilog Hierarchy | |
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| Built-In Logic Primitives | |
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| Latches and Flipflops | |
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| Blocking and Nonblocking Assignments | |
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| Miscellaneous Verilog Syntax Items | |
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| Digital Design Strategies and Techniques | |
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| Design Processing Steps | |
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| Analog Building Blocks for Digital Primitives | |
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| Using a LUT to Implement Logic Functions | |
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| Discussion of Design Processing Steps | |
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| Synchronous Logic Rules | |
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| Clocking Strategies | |
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| Logic Minimization | |
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| What Does the Synthesizer Do? Area Delay Optimization | |
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| A Digital Circuit Toolbox | |
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| Verilog Hierarchy Revisited | |
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| Tristate Signals and Busses | |
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| Bidirectional Busses | |
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| Priority Encoders | |
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| Area Speed Optimization in Synthesis | |
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| Trade-off Between Operating Speed and Latency | |
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| Delays in FPGA Logic Elements | |
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| State Machines | |
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| Adders | |
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| Subtractors | |
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| Multipliers | |
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| More Digital Circuits: Counters, RAMs, and FIFOs | |
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| Ripple Counters | |
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| Johnson Counters | |
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| Linear Feedback Shift Registers | |
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| Cyclic Redundancy Checksums | |
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| ROM | |
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| RAM | |
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| FIFO Notes | |
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| Verilog Test Fixtures | |
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| Compiler Directives | |
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| Automated Testing | |
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| Real World Design: Tools, Techniques, and Trade-offs | |
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| Compiling with LeonardoSpectrum | |
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| Complete Design Flow, 8-Bit Equality Comparator | |
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| 8-Bit Equality Comparator with Hierarchy | |
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| Optimization Options In the Xilinx Environment | |
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| Mapping Options | |
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| Logic Level Timing Report Post Layout Timing Report | |
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| VHDL Verilog Simulation Options | |
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| Other Design Manager Tools | |
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| A Look at Competing Architectures | |
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| Factors that Determine Integrated Circuit Pricing | |
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| FPGA Device Design | |
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| FPGA Technology Selection Checklist | |
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| Xilinx FPGA Architectures | |
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| Altera CPLD Architectures | |
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| Libraries, Reusable Modules, and IP | |
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| Keys to Increased Productivity | |
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| Library Elements | |
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| Structural Coding Style | |
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| A Small Diversion to Compare a Schematic to a Verilog Design | |
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| Using LogiBLOX Module Generator | |
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| Design Reuse, Reusing Your Own Code | |
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| Buying IP Designs | |
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| Summing Up | |
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| Designing for ASIC Conversion | |
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| HardWire Devices | |
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| Semicustom Devices | |
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| Design Rules for ASIC Conversion | |
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| Synchronous Design Rules | |
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| Oscillators | |
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| Delay Lines | |
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| The Language of Test | |
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| Print-on-Change Test Vectors | |
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| Afterword-A Look into the Future | |
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| Resources | |
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| Glossary and Acronyms | |
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| Bibliography | |
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| Index | |
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| The Author | |