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Preface | |
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Introduction | |
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Structured Computer Organization | |
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Languages, Levels, and Virtual Machines | |
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Contemporary Multilevel Machines | |
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Evolution of Multilevel Machines | |
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Milestones in Computer Architecture | |
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The Zeroth Generation-Mechanical Computers (1642-1945) | |
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The First Generation-Vacuum Tubes (1945-1955) | |
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The Second Generation-Transistors (1955-1965) | |
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The Third Generation-Integrated Circuits (1965-1980) | |
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The Fourth Generation-Very Large Scale Integration (1980-?) | |
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The Fifth Generation-Invisible Computers | |
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The Computer Zoo | |
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Technological and Economic Forces | |
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The Computer Spectrum | |
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Disposable Computers | |
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Microcontrollers | |
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Game Computers | |
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Personal Computers | |
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Servers | |
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Collections of Workstations | |
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Mainframes | |
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Example Computer Families | |
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Introduction to the Pentium 4 | |
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Introduction to the UltraSPARC III | |
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Introduction to the 8051 | |
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Metric Units | |
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Outline of This Book | |
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Computer Systems Organization | |
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Processors | |
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CPU Organization | |
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Instruction Execution | |
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RISC versus CISC | |
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Design Principles for Modern Computers | |
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Instruction-Level Parallelism | |
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Processor-Level Parallelism | |
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Primary Memory | |
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Bits | |
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Memory Addresses | |
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Byte Ordering | |
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Error-Correcting Codes | |
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Cache Memory | |
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Memory Packaging and Types | |
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Secondary Memory | |
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Memory Hierarchies | |
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Magnetic Disks | |
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Floppy Disks | |
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IDE Disks | |
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SCSI Disks | |
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RAID | |
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CD-ROMs | |
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CD-Recordables | |
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CD-Rewritables | |
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DVD | |
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Blu-Ray | |
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Input/Output | |
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Buses | |
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Terminals | |
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Mice | |
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Printers | |
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Telecommunications Equipment | |
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Digital Cameras | |
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Character Codes | |
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Summary | |
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The Digital Logic Level | |
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Gates and Boolean Algebra | |
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Gates | |
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Boolean Algebra | |
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Implementation of Boolean Functions | |
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Circuit Equivalence | |
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Basic Digital Logic Circuits | |
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Integrated Circuits | |
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Combinational Circuits | |
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Arithmetic Circuits | |
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Clocks | |
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Memory | |
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Latches | |
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Flip-Flops | |
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Registers | |
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Memory Organization | |
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Memory Chips | |
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RAMs and ROMs | |
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CPU Chips and Buses | |
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CPU Chips | |
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Computer Buses | |
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Bus Width | |
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Bus Clocking | |
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Bus Arbitration | |
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Bus Operations | |
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Example CPU Chips | |
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The Pentium 4 | |
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The UltraSPARC III | |
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The 8051 | |
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Example Buses | |
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The ISA Bus | |
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The PCI Bus | |
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PCI Express | |
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The Universal Serial Bus | |
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Interfacing | |
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I/O Chips | |
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Address Decoding | |
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Summary | |
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The Microarchitecture Level | |
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An Example Microarchitecture | |
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The Data Path | |
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Microinstructions | |
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Microinstruction Control: The Mic-1 | |
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An Example Isa: IJVM | |
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Stacks | |
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The IJVM Memory Model | |
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The IJVM Instruction Set | |
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Compiling Java to IJVM | |
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An Example Implementation | |
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Microinstructions and Notation | |
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Implementation of IJVM Using the Mic-1 | |
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Design of the Microarchitecture Level | |
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Speed versus Cost | |
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Reducing the Execution Path Length | |
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A Design with Prefetching: The Mic-2 | |
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A Pipelined Design: The Mic-3 | |
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A Seven-Stage Pipeline: The Mic-4 | |
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Improving Performance | |
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Cache Memory | |
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Branch Prediction | |
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Out-of-Order Execution and Register Renaming | |
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Speculative Execution | |
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Examples of the Microarchitecture Level | |
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The Microarchitecture of the Pentium 4 CPU | |
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The Microarchitecture of the UltraSPARC-III Cu CPU | |
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The Microarchitecture of the 8051 CPU | |
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Comparison of the Pentium, Ultrasparc, and 8051 | |
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Summary | |
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The Instruction Set Architecture Level | |
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Overview of the ISA Level | |
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Properties of the ISA Level | |
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Memory Models | |
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Registers | |
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Instructions | |
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Overview of the Pentium 4 ISA Level | |
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Overview of the UltraSPARC III ISA Level | |
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Overview of the 8051 ISA Level | |
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Data Types | |
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Numeric Data Types | |
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Nonnumeric Data Types | |
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Data Types on the Pentium 4 | |
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Data Types on the UltraSPARC III | |
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Data Types on the 8051 | |
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Instruction Formats | |
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Design Criteria for Instruction Formats | |
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Expanding Opcodes | |
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The Pentium 4 Instruction Formats | |
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The UltraSPARC III Instruction Formats | |
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The 8051 Instruction Formats | |
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Addressing | |
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Addressing Modes | |
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Immediate Addressing | |
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Direct Addressing | |
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Register Addressing | |
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Register Indirect Addressing | |
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Indexed Addressing | |
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Based-Indexed Addressing | |
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Stack Addressing | |
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Addressing Modes for Branch Instructions | |
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Orthogonality of Opcodes and Addressing Modes | |
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The Pentium 4 Addressing Modes | |
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The UltraSPARC III Addressing Modes | |
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The 8051 Addressing Modes | |
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Discussion of Addressing Modes | |
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Instruction Types | |
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Data Movement Instructions | |
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Dyadic Operations | |
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Monadic Operations | |
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Comparisons and Conditional Branches | |
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Procedure Call Instructions | |
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Loop Control | |
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Input/Output | |
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The Pentium 4 Instructions | |
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The UltraSPARC III Instructions | |
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The 8051 Instructions | |
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Comparison of Instruction Sets | |
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Flow of Control | |
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Sequential Flow of Control and Branches | |
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Procedures | |
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Coroutines | |
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Traps | |
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Interrupts | |
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A Detailed Example: The Towers of Hanoi | |
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The Towers of Hanoi in Pentium 4 Assembly Language | |
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The Towers of Hanoi in UltraSPARC III Assembly Language | |
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The IA-64 Architecture and the Itanium 2 | |
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The Problem with the Pentium 4 | |
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The IA-64 Model: Explicitly Parallel Instruction Computing | |
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Reducing Memory References | |
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Instruction Scheduling | |
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Reducing Conditional Branches: Predication | |
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Speculative Loads | |
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Summary | |
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The Operating System Machine Level | |
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Virtual Memory | |
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Paging | |
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Implementation of Paging | |
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Demand Paging and the Working Set Model | |
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Page Replacement Policy | |
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Page Size and Fragmentation | |
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Segmentation | |
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Implementation of Segmentation | |
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Virtual Memory on the Pentium 4 | |
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Virtual Memory on the UltraSPARC III | |
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Virtual Memory and Caching | |
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Virtual I/O Instructions | |
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Files | |
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Implementation of Virtual I/O Instructions | |
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Directory Management Instructions | |
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Virtual Instructions for Parallel Processing | |
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Process Creation | |
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Race Conditions | |
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Process Synchronization Using Semaphores | |
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Example Operating Systems | |
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Introduction | |
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Examples of Virtual Memory | |
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Examples of Virtual I/O | |
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Examples of Process Management | |
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Summary | |
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The Assembly Language Level | |
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Introduction to Assembly Language | |
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What Is an Assembly Language? | |
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Why Use Assembly Language? | |
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Format of an Assembly Language Statement | |
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Pseudoinstructions | |
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Macros | |
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Macro Definition, Call, and Expansion | |
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Macros with Parameters | |
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Advanced Features | |
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Implementation of a Macro Facility in an Assembler | |
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The Assembly Process | |
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Two-Pass Assemblers | |
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Pass One | |
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Pass Two | |
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The Symbol Table | |
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Linking and Loading | |
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Tasks Performed by the Linker | |
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Structure of an Object Module | |
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Binding Time and Dynamic Relocation | |
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Dynamic Linking | |
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Summary | |
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Parallel Computer Architectures | |
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On-Chip Paralellism | |
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Instruction-Level Parallelism | |
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On-Chip Multithreading | |
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Single-Chip Multiprocessors | |
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Coprocessors | |
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Network Processors | |
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Media Processors | |
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Cryptoprocessors | |
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Shared-Memory Multiprocessors | |
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Multiprocessors vs. Multicomputers | |
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Memory Semantics | |
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UMA Symmetric Multiprocessor Architectures | |
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NUMA Multiprocessors | |
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COMA Multiprocessors | |
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Message-Passing Multicomputers | |
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Interconnection Networks | |
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MPPs-Massively Parallel Processors | |
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Cluster Computing | |
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Communication Software for Multicomputers | |
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Scheduling | |
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Application-Level Shared Memory | |
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Performance | |
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Grid Computing | |
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Summary | |
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Reading List and Bibliography | |
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Suggestions for Further Reading | |
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Introduction and General Works | |
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Computer Systems Organization | |
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The Digital Logic Level | |
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The Microarchitecture Level | |
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The Instruction Set Architecture Level | |
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The Operating System Machine Level | |
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The Assembly Language Level | |
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Parallel Computer Architectures | |
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Binary and Floating-Point Numbers | |
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Assembly Language Programming | |
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Alphabetical Bibliography | |
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Binary Numbers | |
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Finte-Precision Numbers | |
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Radix Number Systems | |
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Conversion From One Radix to Another | |
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Negative Binary Numbers | |
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Binary Arithmetic | |
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Floating-Point Numbers | |
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Principles of Floating Point | |
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IEEE Floating-Point Standard 754 | |
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Assembly Language Programming | |
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Overview | |
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Assembly Language | |
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A Small Assembly Language Program | |
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The 8088 Processor | |
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The Processor Cycle | |
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The General Registers | |
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Pointer Registers | |
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Memory and Addressing | |
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Memory Organization and Segments | |
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Addressing | |
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The 8088 Instruction Set | |
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Move, Copy and Arithmetic | |
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Logical, Bit and Shift Operations | |
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Loop and Repetitive String Operations | |
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Jump and Call Instructions | |
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Subroutine Calls | |
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System Calls and System Subroutines | |
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Final Remarks on the Instruction Set | |
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The Assembler | |
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Introduction | |
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The ACK-Based Tutorial Assembler as88 | |
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Some Differences with Other 8088 Assemblers | |
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The Tracer | |
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Tracer Commands | |
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Getting Started | |
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Examples | |
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Hello World Example | |
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General Registers Example | |
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Call Command and Pointer Registers | |
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Debugging an Array Print Program | |