Computer Architecture A Quantitative Approach

ISBN-10: 0123704901

ISBN-13: 9780123704900

Edition: 4th 2006

List price: $89.95 Buy it from $4.09
eBook available
This item qualifies for FREE shipping

*A minimum purchase of $35 is required. Shipping is provided via FedEx SmartPost® and FedEx Express Saver®. Average delivery time is 1 – 5 business days, but is not guaranteed in that timeframe. Also allow 1 - 2 days for processing. Free shipping is eligible only in the continental United States and excludes Hawaii, Alaska and Puerto Rico. FedEx service marks used by permission."Marketplace" orders are not eligible for free or discounted shipping.

30 day, 100% satisfaction guarantee

If an item you ordered from TextbookRush does not meet your expectations due to an error on our part, simply fill out a return request and then return it by mail within 30 days of ordering it for a full refund of item cost.

Learn more about our returns policy

Description: The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of "Computer Architecture," the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability. CD System Requirements "PDF Viewer" The CD material includes PDF documents that you can read with a PDF viewer such as Adobe, Acrobat or Adobe Reader. Recent versions of Adobe Reader for some platforms are included on the CD. "HTML Browser" The navigation framework on this CD is delivered in HTML and JavaScript. It is recommended that you install the latest version of your favorite HTML browser to view this CD. The content has been verified under Windows XP with the following browsers: Internet Explorer 6.0, Firefox 1.5; under Mac OS X (Panther) with the following browsers: Internet Explorer 5.2, Firefox 1.0.6, Safari 1.3; and under Mandriva Linux 2006 with the following browsers: Firefox 1.0.6, Konqueror 3.4.2, Mozilla 1.7.11. The content is designed to be viewed in a browser window that is at least 720 pixels wide. You may find thecontent does not display well if your display is not set to at least 1024x768 pixel resolution. "Operating System" This CD can be used under any operating system that includes an HTML browser and a PDF viewer. This includes Windows, Mac OS, and most Linux and Unix systems. Increased coverage on achieving parallelism with multiprocessors. Case studies of latest technology from industry including the Sun Niagara Multiprocessor, AMD Opteron, and Pentium 4. Three review appendices, included in the printed volume, review the basic and intermediate principles the main text relies upon. Eight reference appendices, collected on the CD, cover a range of topics including specific architectures, embedded systems, application specific processors--some guest authored by subject experts.

Used Starting from $40.20
eBooks Starting from $89.95
Buy eBooks
what's this?
Rush Rewards U
Members Receive:
coins
coins
You have reached 400 XP and carrot coins. That is the daily max!

Study Briefs

Limited time offer: Get the first one free! (?)

All the information you need in one place! Each Study Brief is a summary of one specific subject; facts, figures, and explanations to help you learn faster.

Add to cart
Study Briefs
SQL Online content $4.95 $1.99
Add to cart
Study Briefs
MS Excel® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS Word® 2010 Online content $4.95 $1.99
Add to cart
Study Briefs
MS PowerPoint® 2010 Online content $4.95 $1.99

Customers also bought

Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading
Loading

Book details

List price: $89.95
Edition: 4th
Copyright year: 2006
Publisher: Elsevier Science & Technology Books
Publication date: 9/13/2006
Binding: Paperback
Pages: 704
Size: 7.50" wide x 9.00" long x 1.00" tall
Weight: 2.904
Language: English

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM's 801 and Stanford's MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

Fundamentals of Computer Design
Introduction
The Changing Face of Computing and the Task of the Computer Designer
Technology Trends
Cost, Price, and their Trends
Measuring and Reporting Performance
Quantitative Principles of Computer Design
Putting It All Together: Performance and Price-Performance
Another View: Power Consumption and Efficiency as the Metric
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises
Instruction Set Principles and Examples
Introduction
Classifying Instruction Set Architectures
Memory Addressing
Addressing Modes for Signal Processing
Type and Size of Operands
Operands for Media and Signal Processing
Operations in the Instruction Set
Operations for Media and Signal Processing
Instructions for Control Flow
Encoding an Instruction Set
Crosscutting Issues: The Role of Compilers
Putting It All Together: The MIPS Architecture
Another View: The Trimedia TM32 CPU
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises
Instruction-Level Parallelism and its Dynamic Exploitation
Instruction-Level Parallelism: Concepts and Challenges
Overcoming Data Hazards with Dynamic Scheduling
Dynamic Scheduling: Examples and the Algorithm
Reducing Branch Costs with Dynamic Hardware Prediction
High Performance Instruction Delivery
Taking Advantage of More ILP with Multiple Issue
Hardware Based Speculation
Studies of the Limitations of ILP
Limitations on ILP for Realizable Processors
Putting It All Together: The P6 Microarchitecture
Another View: Thread Level Parallelism
Crosscutting Issues: Using an ILP Datapath to Exploit TLP
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises
Exploiting Instruction Level Parallelism with Software Approaches
Basic Compiler Techniques for Exposing ILP
Static Branch Prediction
Static Multiple Issue: the VLIW Approach
Advanced Compiler Support for Exposing and Exploiting ILP
Hardware Support for Exposing More Parallelism at Compile-Time
Crosscutting Issues
Putting It All Together: The Intel IA-64 Architecture and Itanium Processor
Another View: ILP in the Embedded and Mobile Markets
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises
Memory-Hierarchy Design
Introduction
Review of the ABCs of Caches
Cache Performance
Reducing Cache Miss Penalty
Reducing Miss Rate
Reducing Cache Miss Penalty or Miss Rate via Parallelism
Reducing Hit Time
Main Memory and Organizations for Improving Performance
Memory Technology
Virtual Memory
Protection and Examples of Virtual Memory
Crosscutting Issues in the Design of Memory Hierarchies
Putting It All Together: Alpha 21264 Memory Hierarchy
Another View: The Emotion Engine of the Sony Playstation 2
Another View: The Sun Fire 6800 Server
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises
Multiprocessors and Thread-Level Parallelism
Introduction
Characteristics of Application Domains
Symmetric Shared-Memory Architectures
Performance of Symmetric Shared-Memory Multiprocessors
Distributed Shared-Memory Architectures
Performance of Distributed Shared-Memory Multiprocessors
Synchronization
Models of Memory Consistency: An Introduction
Multithreading: Exploiting Thread-Level Parallelism within a Processor
Crosscutting Issues
Putting It All Together: Sun''s Wildfire Prototype
Another View: Multithreading in a Commercial Server
Another View: Embedded Multiprocessors
Fallacies and Pitfalls
Concluding Remarks
Historical Perspective and References Exercises Cha
×
Free shipping on orders over $35*

*A minimum purchase of $35 is required. Shipping is provided via FedEx SmartPost® and FedEx Express Saver®. Average delivery time is 1 – 5 business days, but is not guaranteed in that timeframe. Also allow 1 - 2 days for processing. Free shipping is eligible only in the continental United States and excludes Hawaii, Alaska and Puerto Rico. FedEx service marks used by permission."Marketplace" orders are not eligible for free or discounted shipping.

Learn more about the TextbookRush Marketplace.

×