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Through-Silicon Vias for 3D Integration

Best in textbook rentals since 2012!

ISBN-10: 0071785140

ISBN-13: 9780071785143

Edition: 2012

Authors: John H. Lau

List price: $179.00
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Description:

The latest cost- and space-saving methods of 3D integrated circuitsThrough-Silicon Vias (TSVs) for 3D Integrationcovers cutting-edge developments in 3D ICs—essential for the development of low-cost, high-performance electronic and optoelectronic products. The book proposes that every chip or interposer could have two surfaces with circuits.This detailed guide discusses TSV manufacturing yield and hidden costs and includes characterization and reliability data for 3D IC integration. The in-depth information in the book provides context for choosing robust, reliable, high-performance, cost-effective packaging and 3D IC/Si integration techniques for high-density electronic…    
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Book details

List price: $179.00
Copyright year: 2012
Publisher: McGraw-Hill Education
Publication date: 10/11/2012
Binding: Hardcover
Pages: 512
Size: 6.30" wide x 9.30" long x 0.90" tall
Weight: 1.782
Language: English

John Lau graduated with a first class honours in womenswear design at London College of Fashion and has a masters in enterprise. John has worked in various roles within the fashion industry and has experience as a fashion stylist and writer for the international magazines Loaded and the Chinese edition of Vogue. He has helped new brands develop their creative and business direction both in the UK, Hong Kong and China, and continues to have an active role in fashion as a consultant for retail, branding, production and distribution.John is currently a Senior Lecturer in International Fashion Business at Manchester Metropolitan University, teaching on the Fashion Buying and Clothing Design and…    

Foreword
Preface
Acknowledgments
Nanotechnology and 3D Integration for the Semiconductor Industry
Introduction
Nanotechnology
Origin of Nanotechnology
Important Milestones of Nanotechnology
Why Graphene Is So Exciting and Could Be Very Important for the Electronics Industry
Outlook of Nanotechnology
Moore's Law: Nanotechnology for the Electronics Industry
Three-Dimensional Integration
Through-Silicon Via Technology
Origin of 3D Integration
Challenges and Outlook of 3D Si Integration
3D Si Integration
3D Si Integration Bonding Assembly
3D Si Integration Challenges
3D Si Integration Outlooks
Potential Applications and Challenges of 3D IC Integration
Definition of 3D IC Integration
Future Requirements of Mobile Products
Definition of Bandwidth and Wide I/O
Memory Bandwidth
Memory-Chip Stacking
Wide I/O Memory
Wide I/O DRAM
Wide I/O Interface
2.5D and 3D IC Integration (Passive and Active Interposers)
Recent Advances of 2.5D IC Integration (Interposers)
Interposer Used as Intermediate Substrate
Interposer Used as a Stress-Relief (Reliability) Buffer
Interposer Used as Carrier
Interposer Used as a Thermal Management Tool
New Trends in TSV Passive Interposers for 3D IC Integration
Interposer (with a Cavity) Supporting High-Power Chips on Its Top Side and Low-Power Chips on Its Bottom Side
Interposer (on an Organic Substrate with a Cavity) Supporting High-Power Chips on Its Top Side and Low-Power Chip Stacking on Its Bottom Side
A Simple Design Example
Interposer (on an Organic Substrate with a Cavity) Supporting High-Power Chips on the Top Side and Low-Power Chips (with Heat Slug/Spreader) on the Bottom Side
Ultralow-Cost Interposer for 3D IC Integration
Interposer Used as a Thermal Management Tool for 3D IC Integration
Interposer with Embedded Fluidic Microchannels for 3D Light-Ermtting Diode and IC Integration SiP
Embedded 3D IC Integration
Semiembedded Interposer with Stress-Relief Gap
Embedded 3D Hybrid IC Integration for Optoelectronic Interconnects
Summary and Recommendations
TSV Patents
References
General Readings
TSV and 3D Integration and Reliability
3D MEMS and IC Integration
Semiconductor IC Packaging
Through-Silicon Via Technology
Introduction
Who Invented TSV and When
High-Volume Products with TSV Technology
Via Forming
DRD3 versus Laser Drilling
Tapered Via by DRIE
Straight Via by DPIE
Dielectric Isolation Layer (Oxide Liner) Deposition
Tapered Oxide Liner by Thermal Oxidation
Tapered Oxide Liner by PECVD
DoE for Straight Oxide Liner by PECVD
DoE Results for Straight Oxide Liner by PECVD
Summary and Recommendations
Barrier (Adhesion) Layer and Seed (Metal) Layer Deposition
Tapered TSV with Ti Barrier Layer and Cu Seed Layer
Straight TSV with Ta Barrier Layer and Cu Seed Layer
Straight TSV with Ta Barrier Layer Experiments and Results
Straight TSV with Cu Seed Layer Experiments and Results
Summary and Recommendations
TSV Filling by Cu Plating
Cu Plating to Fill Tapered TSVs
Cu Plating to Fill Straight TSVs
Leakage Current Test of Blind Straight TSVs
Summary and Recommendations
Chemical-Mechanical Polishing of Cu Plating Residues
CMP for Tapered TSVs
CMP for Straight TSVs
Summary and Recommendations
TSVCu Reveal
TSVCu Reveal by CMP (Wet Process)
Cu Reveal by Dry Etching Process
Summary and Recommendation
FEOL and BEOL
TSV Processes
Via-Before Bonding Process
Via-After Bonding Process
Via-First Process
Via-Middle Process
Via-Last (From the Front Side) Process
Via-Last (From the Backside) Process
How About the Passive Interposers?
Summary and Recommendations
References
Through-Silicon Vias: Mechanical, Thermal, and Electrical Behaviors
Introduction
Mechanical Behavior, of TSVs in System-in-Package
Mechanical Behavior of TSVs for Active/Passive Interposers
DFR Results
TSVs with a Redistribution Layer
Summary and Recommendations
Mechanical Behavior of TSVs in Memory-Chip Stacking
Boundary-Value Problem
Nonlinear Thermal Stress Analyses for TSVs
Modified Virtual Crack-Closure Technique
Energy Release Rate Estimation for TSVs
Parametric Study of Energy Release Rate for TSVs
Summary and Recommendations
Thermal Behaviors of TSVs
Equivalent Thermal Conductivity of TSV Chip/Interposer
Effect of TSV Pitch on Equivalent Thermal Conductivity of Chip/Interposer
Effect of TSV Filler on Equivalent Thermal Conductivity of Chip/Interposer
Effect of Plating Thickness of a Partially Cu-Filled TSV Interposer /Chip on the Equivalent Thermal Conductivity
More Accurate Models
Summary and Recommendations
Electrical Modeling of TSVs
Definition
The Model and Equations
Summary and Recommendations
Electrical Test of Blind TSVs
Motivation
Testing Principle and Apparatus
Experimental Procedures, Measurements, and Results
Blind TSV Electrical Test Guidelines
Summary and Recommendations
References
Thin-Wafer Strength Measurement
Introduction
Piezoresistive Stress Sensors for Thin-Wafer Strength Measurement
Problem Definition
Design and Fabrication of Piezoresistive Stress Sensors
Calibration of Stress Sensors
Stresses in Wafers after Thinning (Back-Grinding)
Stresses in Wafers after Mounting on Dicing Tape
Summary and Recommendations
Effects of Wafer Back-Grinding on the Mechanical Behavior of Cu-Low-k Chips
Problem Definition
Experiments
Results and Discussion
Summary and Recommendations
References
Thin-Wafer Handling
Introduction
Wafer Thinning and Thin-Wafer Handling
Adhesive Is the Key
Thin-Wafer Handling Issues and Potential Solutions
Thin-Wafer Handling of 200-mm Wafers
Thin-Wafer Handling of 300-mm Wafers
Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu/Au Pads
Effect of Dicing Tape on Thin-Wafer Handling of Wafers with Cu-Ni-Au UBMs
Effect of Dicing Tape on Thin-Wafer Handling of Interposer with RDLs and Ordinary Solder Bumps
Materials and Equipments for Thin-Wafer Handling
Adhesive and Process Guidelines for Thin-Water Handling
Some Requirements for Selecting Adhesives
Some Process Guideline for Thin-Wafer Handling
Summary and Recommendations
3M Wafer Support System
EVG's Temporary Bonding and Debonding System
Temporary Bonding
Debonding
Thin-Wafer Handling with Carrierless Technology
The Idea
The Design and Process
Summary and Recommendations
References
Microbumping, Assembly, and Reliability
Introduction
Can we Apply the Wafer Bumping Method of Ordinary Solder Bumps to Solder Microbumps?
Problem Definition
Electroplating Method for Wafer Bumping of Ordinary Solder Bumps
Assembly of 3D IC Integration SiPs
Electroplating Method for Wafer Bumping of Solder Microbumps
Test Vehicle
Wafer Microbumping of the Test Wafer by Conformal Cu Plating and Electroplating Sn
Wafer Microbumping of the Test Wafer by Nonconf ormal Cu Plating and Electroplating of Sn
Can We Apply the Same Parameters of the Electroplating Method for Ordinary Solder Bumps to Microbumps?
Summary and Recommendations
Wafer Bumping, Assembly, and Reliability Assessments of Ultrafine-Pitch Solder Microbumps
Lead-Free Fine-Pitch Solder Microbumping
Test Vehicle
Microbump Fabrication
Characterization of Microbumps
Lead-Free Fine-Pitch C2C Solder Microbump Assembly
Assembly, Characterization, and Reliability-Assessment Methods
Assembly Process (C2C Natural Reflow)
Characterization of C2C Reflow Assembly Results
Assembly Process (C2C Thermocompression Bonding)
Characterization of C2C TCB Assembly Results
Reliability Assessments of Assemblies
Wafer Bumping of Lead-Free Ultrafine-Pitch Solder Microbumps
Test Vehicle
Microbump Fabrication
Characterization of Ultrafine-Pitch Microbumps
Conclusions and Recommendations
References
Microbump Electromigration
Introduction
Solder Micro-joints with Larger Solder Volumes and Pitch
Test Vehicles and Methods
Test Procedures
Microstructures of Samples Before Tests
Samples Tested at 140�C with Low Current Density
Samples Tested at 140�C with High Current Density
Failure Mechanism of the Multiphase Solder-Joint Interconnect
Summary and Recommendations
Solder Microjoints with Smaller Volumes and Pitches
Experimental Setup and Procedure
Results and Discussion
Summary and Recommendations
References
Transient Liquid-Phase Bonding: Chip-to-Chip, Chip-to-Wafer, and Water-to-Wafer
Introduction
How Does Low-Temperature Bonding with Solder Work?
Low-Temperature C2C [(SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub>/Ti/Cu) to (SiO<sub>2</sub>/Si<sub>3</sub>N<sub>4</sub>/Ti/Cu/In/Sn/Au)] Bonding
Test Vehicle
Pull-Test Results
X-Ray Diffraction and Transmission Electron Microscope Observations
Low-Temperature C2C [(SiO<sub>2</sub>/Ti/Cu/Au/Sn/In/Sn/Au) to (SiO<sub>2</sub>/Ti/Cu/Sn/In/Sn/Au)] Bonding
Test Vehicle
Qualification Test Results
Low-Temperature C2W [(SiO<sub>2</sub>/Ti/Au/Sn/In/Au) to (SiO<sub>2</sub>/Ti/Au)] Bonding
Solder Design
Test Vehicle
3D IC Chip Stacking with InSnAu Low-Temperature Bonding
SEM, TEM, XDR, and DSC of the InSnAuIMCs
Young's Modulus and Hardness of the InSnAu IMCs
Three Reflows of the InSnAu IMCs
Shear Strength of the InSnAu IMCs
Electrical Resistance of the InSnAu IMCs
When Does the InSnAu IMC Become Unstable?
Summary and Recommendations
Low-Temperature W2W [TiCuTiAu to TiCuTiAuSnlnSrunAu] Bonding
Test Vehicle
Test Vehicle Fabrication
Low-Temperature W2W Bonding
C-SAM Inspection
Microstructure by SEM/EDX/ FIB/TEM
Helium Leak-Rate Test and Results
Reliability Tests and Results
Summary and Recommendations
References
Thermal Management of Three-Dimensional Integrated Circuit Integration
Introduction
Effects of TSV Interposer on Thermal Performance of 3D Integration SiPs
Geometry and Thermal Properties of Materials for Package Modeling
Effect of TSV Interposer on Package Thermal Resistance
Effect of Chip Power
Effect of Interposer Size
Effect of TSV Interposer Thickness
Effect of Moore's Law Chip Size
Thermal Performance of 3D Memory-Chip Stacking
Thermal Performance of 3D Stacked TSV Chips with a Uniform Heat Source
Thermal Performance of 3D Stacked TSV Chips with a Nonuniform Heat Source
Two TSV Chips (Each with One Distinct Heat Source)
Two TSV Chips (Each with Two Distinct Heat Sources)
Two TSV Chips with Two Staggered Distinct Heat Sources
Effect of Thickness of the TSV Chip on Its Hot-Spot Temperature
Summary and Recommendations
Thermal Management System with TSVs and Microchannels for 3D Integration SiPs
Test Vehicle
Test Vehicle Fabrication
Wafer-to-Wafer Bonding
Thermal and Electrical Performance
Quality and Reliability
Summary and Recommendations
References
Three-Dimensional Integrated Circuit Packaging
Introduction
Cost: TSV Technology versus Wire-Bonding Technology
Wire Bonding of Stack Dies on Cu-Low-fc Chips
Test Vehicles
Stresses at the Cu-Low-fc Pads
Assembly and Process
Summary and Recommendations
Bare Chip-to-Chip and Face-to-Face Interconnects
3D IC Packaging with AuSn Interconnects
Test Vehicle and Fabrication
Chip-to-Wafer Assembly
C2W Design of Experiments (DoE)
Reliability Tests and Results
3D IC Packaging with SnAg Interconnects
Summary and Recommendations
Low-Cost, High-Performance, and High-Density SiPs with Face-to-Face Interconnects
Cu Wire-Interconnect Technology for Moore's Law Chips with Ultrafine-PitchCu-Low-k Pads
Reliability Assessment of Ultrafine-Pitch Cu-Low-k Pads with Cu WIT
A Few New Design Proposals
Fan-Out-Embedded WLP-to-Chip (Face-to-Face) Interconnects
2DeWLP/RCP
3DeWLP/RCP
Summary and Recommendation
A Note on Wire-Bonding Reliability
Common Chip-Level Interconnects
Boundary-Value Problem
Numerical Results
Experimental Results
More Results on Cu Wires
Results on Au Wires
Stress-Strain Relationship of Cu and Au Wires
Summary arid Recommendations
References
Future Trends of 3D Integration
Introduction
The Trend of 3D Si Integration
The Trend of 3D IC Integration
References
Index
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