Signal and Power Integrity in Digital Systems TTL, CMOS, and BICMOS

Name: Signal and Power Integrity in Digital Systems TTL, CMOS, and BICMOS
Price: 27.73 USD
Availability: InStock
ISBN: 9780070087347

ISBN-10: 0070087342

ISBN-13: 9780070087347

Edition: 1996

Authors: James E. Buchanan, Bert D. Buchanan

List price: $65.95

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Book details

List price: $65.95
Copyright year: 1996
Publisher: McGraw-Hill Professional Publishing
Binding: Hardcover
Pages: 381
Size: 6.25" wide x 9.50" long x 1.25" tall
Weight: 1.496
Language: English



Preface


Acknowledgments



Introduction


References



Advanced Schottky TTL, Advanced CMOS, and BiCMOS Logic Families



High-Performance Logic Families



Advanced Schottky TTL Logic Families



Advanced CMOS Logic Families



BiCMOS Logic Families



Timing Specifications



Comparison of Dynamic Operational Characteristics



Timing Parameter Adjustments for Worst-Case Conditions



Caution: Beware of FMAX



Static Input-Output Characteristics



Input Voltage Levels



Input Currents



Output Voltage Levels



Compatibility of Logic Families



Common Groupd, Common Supply Voltage, and TTL Input and Output Levels



Common Ground, Common Supply Voltage, CMOS Inputs, and TTL Outputs



Common Ground, Common Supply Voltage, TTL Inputs, and CMOS Outputs



Common Ground, Different Supply Voltage Levels



Dynamic Interface Issues



CMOS or TTL Levels?



Noise Margins of Logic Families



Static Noise Margins of Advanced Schottky TTL Families



Static Noise Margins of Advanced CMOS Logic Families



Static Noise Margins of BiCMOS Logic Families



Dynamic Noise Immunity



Noise Margin Summary



References



Bibliography



Advanced Schottky TTL, CMOS, and BiCMOS Logic Circuits



Advanced Schottky TTL Circuits



Equivalent Circuits for Diodes and Transistors



Functional Operation of the TTL NAND Gate



Advanced CMOS Logic Circuits



BiCMOS Logic Circuits



No Opens or Intermediate Logic Levels on CMOS or BiCMOS Inputs



Latch-up and Latch-up Prevention



Electrostatic Discharge Protection



References



Inductance and Transient Switching Currents



Inductance



Physical and Electrical Factors that Influence Inductance



Transient Voltage Drop across inductors



Transient Switching Currents



Transient Internal Switching Currents



Transient Load Currents



Ground Bounce



Guidelines for Reducing Inductance and Transient-Current Effects



References



Power Distribution



Component Power and Ground-Pin Connections to Power and Ground Planes



Voltage Loss across Planes



DC Loss



AC Loss



Circuit-Board-to-Motherboard Connections



Power-Supply-to-Motherboard Connections



Voltage Loss in Power Conductors



Voltage Loss in Power Connections



Connections between Dissimilar Metals



Overvoltage Protection



System Grounding



Decoupling Capacitors



Local Decoupling



Bulk Decoupling



Summary of Power Distribution Requirements



Summary of Techniques for Minimizing Inductance and Transient-Current Effects in Power Distribution Networks



References



Signal Interconnections



Signal Interconnections Categories



Physical Means of Interconnecting Signals



Component-to-Component Connections



Board-to-Board Connections



Unit-to-unit Connections



Interconnection Impedance



Loaded Transmission-Line Impedance



High-Density Multilayer PC Boards



Characteristic Impedance of Some Common Interconnection Structures



Breadboard Interconnections



Routing Guidelines



Crosstalk



Signal Interconnection Summary



References



Bibliography



Transmission-Line Effects



Basic Transmission-Line Theory



Ideal Transmission-Line Response



Transmission-Line Termination



TTL, CMOS, and BiCMOS Device Transmission-Line Response



Typical Advanced CMOS Device Transmission-Line Response



Typical TTL and BiCMOS Device Transmission-Line Response



Controlling Undershoot



Optimum Source-Load Impedance Characteristics



Driver-Receiver Response Test Circuit



Summary of Techniques for Dealing with Transmission-Line Effects



References



Bibliography



Clock Distribution



Universal Clock Distribution Guidelines



Board Level Clock Distribution



Board-to-Board Clock Distribution



Unit-to-Unit Clock Distribution



Test Clock Input Port



References



Bibliography



Device, Board, and Unit Interfaces



Component-to-Component Interfaces



Input Level Requirements



Unused Inputs



Derating Current Drive Specifications



Increasing Drive Capability



Board-to-Board Interfaces



Bus Interfaces



General Requirements for Three-State Buses



Board and System Interface Guidelines



Board and System Interface Protection



Signal Interfaces between Remote Units



Differential Unit-to-Unit Signal Transmission



Low-Speed Unit-to-Unit Signal Transmission



Very Low-Speed Unit-to-Unit Signal Transmission



Unit-to-Unit Line Terminations



Miscellaneous Unit-to-Unit Considerations



Summary of Interface Guidelines



References



Noise-Tolerant Logic Architectures



Synchronous Design



Important Synchronous Design Issues



Clock Requirements



Hold-Time Requirements



Synchronizing Asynchronous Inputs



Devices Incompatible with Synchronous Design



One-Shots



Latches



Master-Slave Devices



Summary of Synchronous Design Practices



References



Bibliography



Worst-Case Timing



Device Delays



Device Timing Specifications



Timing Parameter Adjustments for Worst-Case Conditions



Caution: Beware of FMAX



Circuit Board Interconnection Delays



Interconnecting Line Propagation Delay



Line Propagation Delay with Distributed Loads



Line Delay due to Transmission-Line Effects



Backpanel Interconnection Delays



Unit-to-Unit Interconnection Timing



Examples of Worst-Case Timing



Signal Timing Summary



Signal Timing Checklist



References



System Initialization and Low-Voltage Sensing



Initialization Signal Generation



Reset Signal Distribution



Reset Signal Phasing



Reset Signal Loading



Reset Signal Timing



Write Protection of Nonvolatile Memories



Logic Initialization to Prevent Hazardous or Damaging Conditions



Summary of Initialization and Low-Voltage Sensing Techniques



References



Memory Subsystem Design



Semiconductor Memory Devices



Typical Memory Device



High-Speed Advanced CMOS and BiCMOS Memory Devices



High-Speed Memory Subsystem Design



Typical Memory Subsystem



Memory Circuit Layout



Control Signal Generation and Timing



Memory Worst-Case Timing Analysis



Crosstalk Control



Data Bus Contention Prevention



Power and Ground Distribution and Decoupling



Failure Rates and Error Detection and Correction



Memory Subsystem Testing



Summary of High-Speed Memory Design Techniques



References



Bibliography



Using PLDs, FIFOs, and Other LSI Devices



PLD Application Tips



FIFO Application Tips



Important Considerations in the Use of LSI Devices



Ground-Bounce and Output Pin Interaction



Proper Connection of Unused Inputs



Proper Termination of Inputs



Decoupling Needs of LSI Devices



Summary of Design Techniques for PLDs, FIFOs, and Other LSI Devices



References



ASIC Application Tips



Logic structures to Avoid in ASICs



Guidelines for Selecting Input-Output Characteristics



CMOS or TTL Levels?



Do Not Let CMOS or BiCMOS ASIC Inputs Float



Output Drive Selection



Early Determination of Number of Ground and Power Pins



Guidelines for Interface Timing



Summary of System Application Tips for ASICs



References



Bibliography


Appendix



Conversion Factors



Definition of Symbols and Acronyms



Trademarks



CMOS and BiCMOS Power Dissipation Calculations



Quiescent Power Dissipation Calculations



Dynamic Power Dissipation Calculations



References


Glossary


Index